Lines Matching full:messaging

505 **     Messaging Unit (MU) of Type A processor
569 **      Messaging Unit (MU) of Type B processor(MARVEL)
588 **      Messaging Unit (MU) of Type C processor(LSI)
663 **      Messaging Unit (MU) of Type D processor
732 **      Messaging Unit (MU) of Type E processor(LSI)
810 **      Messaging Unit (MU) of Type F processor(LSI)
2775 **  							Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-t…
2904 …4 Kbytes of memory defined by the IABAR0, IAUBAR0 and the IALR0 is reserved for the Messaging Unit.
3254 …irst 4 Kbytes of the ATU inbound address translation window 0 are reserved for the Messaging Unit. 
4686 **                 Messaging Unit (MU) of the Intel R 80331 I/O processor (80331)
4688 **	The Messaging Unit (MU) transfers data between the PCI system and the 80331 
4690 **	The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translatio…
4694 **	All of the Messaging Unit errors are reported in the same manner as ATU errors. 
4755 **  .  The MU has four independent messaging mechanisms.
4777 **     Each interrupt generated by the Messaging Unit can be masked.
4779 **  .  Multi-DWORD PCI burst accesses are not supported by the Messaging Unit, 
4790 **  .  All registers needed to configure and control the Messaging Unit are memory-mapped registers.
4795 **  .  From the PCI perspective, the Messaging Unit is part of the Address Translation Unit.
4796 **     The Messaging Unit uses the PCI configuration registers of the ATU for control and status in…
4797 **     The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Con…
4798 **     The Messaging Unit reports all PCI errors in the ATU Status Register.
4800 **  .  Parts of the Messaging Unit can be accessed as a 64-bit PCI device. 
4878 **    The Inbound Interrupt Mask Register affects only the generation of the normal messaging unit …
4889 **    All other bits, when set, cause the Normal Messaging Unit interrupt line of the Intel XScale …
4906 **    All interrupts are routed to the Normal Messaging Unit interrupt input of the Intel XScale co…
4908 **    these two are routed to the Messaging Unit Error interrupt input. 
4948 … (IIMR) provides the ability to mask Intel XScale core interrupts generated by the Messaging Unit. 
5044 **  interrupts generated by the Messaging Unit. Each bit in the mask register corresponds to a
5141 **    The head and tail pointers are incremented by either the Intel XScale core or the Messaging U…
5147 **  Messaging Unit...
5149 **  The Messaging Unit generates an interrupt to the Intel XScale core or generate a PCI interrupt …
5338 **    Messaging Unit Internal Bus Memory Map