Lines Matching +full:0 +full:x1280
64 #define FALSE 0
67 # define INTR_ENTROPY 0
71 #define offsetof(type, member) ((size_t)(&((type *)0)->member))
87 #define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */
88 #define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */
89 #define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */
90 #define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */
91 #define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */
92 #define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */
93 #define PCI_DEVICE_ID_ARECA_1200 0x1200 /* Device ID */
94 #define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */
95 #define PCI_DEVICE_ID_ARECA_1203 0x1203 /* Device ID */
96 #define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */
97 #define PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID */
98 #define PCI_DEVICE_ID_ARECA_1214 0x1214 /* Device ID */
99 #define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */
100 #define PCI_DEVICE_ID_ARECA_1222 0x1222 /* Device ID */
101 #define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */
102 #define PCI_DEVICE_ID_ARECA_1231 0x1231 /* Device ID */
103 #define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */
104 #define PCI_DEVICE_ID_ARECA_1261 0x1261 /* Device ID */
105 #define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */
106 #define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */
107 #define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */
108 #define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */
109 #define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */
110 #define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */
111 #define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */
112 #define PCI_DEVICE_ID_ARECA_1883 0x1883 /* Device ID */
113 #define PCI_DEVICE_ID_ARECA_1884 0x1884 /* Device ID */
115 #define ARECA_SUB_DEV_ID_1880 0x1880 /* Subsystem Device ID */
116 #define ARECA_SUB_DEV_ID_1882 0x1882 /* Subsystem Device ID */
117 #define ARECA_SUB_DEV_ID_1883 0x1883 /* Subsystem Device ID */
118 #define ARECA_SUB_DEV_ID_1884 0x1884 /* Subsystem Device ID */
119 #define ARECA_SUB_DEV_ID_1212 0x1212 /* Subsystem Device ID */
120 #define ARECA_SUB_DEV_ID_1213 0x1213 /* Subsystem Device ID */
121 #define ARECA_SUB_DEV_ID_1214 0x1214 /* Subsystem Device ID */
122 #define ARECA_SUB_DEV_ID_1216 0x1216 /* Subsystem Device ID */
123 #define ARECA_SUB_DEV_ID_1222 0x1222 /* Subsystem Device ID */
124 #define ARECA_SUB_DEV_ID_1223 0x1223 /* Subsystem Device ID */
125 #define ARECA_SUB_DEV_ID_1224 0x1224 /* Subsystem Device ID */
126 #define ARECA_SUB_DEV_ID_1226 0x1226 /* Subsystem Device ID */
128 #define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */
129 #define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */
130 #define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */
131 #define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */
132 #define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */
133 #define PCIDevVenIDARC1200 0x120017D3 /* Vendor Device ID */
134 #define PCIDevVenIDARC1201 0x120117D3 /* Vendor Device ID */
135 #define PCIDevVenIDARC1203 0x120317D3 /* Vendor Device ID */
136 #define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */
137 #define PCIDevVenIDARC1212 0x121217D3 /* Vendor Device ID */
138 #define PCIDevVenIDARC1213 0x121317D3 /* Vendor Device ID */
139 #define PCIDevVenIDARC1214 0x121417D3 /* Vendor Device ID */
140 #define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */
141 #define PCIDevVenIDARC1222 0x122217D3 /* Vendor Device ID */
142 #define PCIDevVenIDARC1223 0x122317D3 /* Vendor Device ID */
143 #define PCIDevVenIDARC1224 0x122417D3 /* Vendor Device ID */
144 #define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */
145 #define PCIDevVenIDARC1231 0x123117D3 /* Vendor Device ID */
146 #define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */
147 #define PCIDevVenIDARC1261 0x126117D3 /* Vendor Device ID */
148 #define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */
149 #define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */
150 #define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */
151 #define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */
152 #define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */
153 #define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */
154 #define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */
155 #define PCIDevVenIDARC1882 0x188217D3 /* Vendor Device ID */
156 #define PCIDevVenIDARC1883 0x188317D3 /* Vendor Device ID */
157 #define PCIDevVenIDARC1884 0x188417D3 /* Vendor Device ID */
158 #define PCIDevVenIDARC1886_0 0x188617D3 /* Vendor Device ID */
159 #define PCIDevVenIDARC1886_ 0x188917D3 /* Vendor Device ID */
160 #define PCIDevVenIDARC1886 0x188A17D3 /* Vendor Device ID */
163 #define PCIR_BARS 0x10
167 #define PCI_BASE_ADDR0 0x10
168 #define PCI_BASE_ADDR1 0x14
169 #define PCI_BASE_ADDR2 0x18
170 #define PCI_BASE_ADDR3 0x1C
171 #define PCI_BASE_ADDR4 0x20
172 #define PCI_BASE_ADDR5 0x24
178 #define ARCMSR_SCSICMD_IOCTL 0x77
179 #define ARCMSR_CDEVSW_IOCTL 0x88
180 #define ARCMSR_MESSAGE_FAIL 0x0001
181 #define ARCMSR_MESSAGE_SUCCESS 0x0000
190 #define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff)
223 #define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001
224 #define ARCMSR_IOP_ERROR_VENDORID 0x0002
225 #define ARCMSR_IOP_ERROR_DEVICEID 0x0002
226 #define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003
227 #define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004
228 #define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005
229 #define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006
230 #define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007
231 #define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008
232 #define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009
233 #define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A
236 #define ARECA_SATA_RAID 0x90000000
239 #define FUNCTION_READ_RQBUFFER 0x0801
240 #define FUNCTION_WRITE_WQBUFFER 0x0802
241 #define FUNCTION_CLEAR_RQBUFFER 0x0803
242 #define FUNCTION_CLEAR_WQBUFFER 0x0804
243 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805
244 #define FUNCTION_REQUEST_RETURNCODE_3F 0x0806
245 #define FUNCTION_SAY_HELLO 0x0807
246 #define FUNCTION_SAY_GOODBYE 0x0808
247 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809
265 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001
266 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006
267 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F
268 #define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON 0x00000088
275 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
276 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063
278 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000
279 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001
280 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002
281 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003
282 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004
283 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005
284 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006
285 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007
286 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008
288 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001
289 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002
290 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001
291 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002
293 #define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000
294 #define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000
295 #define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000
296 #define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000
297 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0 0x10000000
298 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1 0x00000001
300 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
302 #define ARCMSR_ARC1680_BUS_RESET 0x00000003
309 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400 /* window of "instruction flags" from…
310 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404
311 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408 /* window of "instruction flags" from…
312 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C
314 #define ARCMSR_IOP2DRV_DOORBELL_1203 0x00021870 /* window of "instruction flags" from…
315 #define ARCMSR_IOP2DRV_DOORBELL_MASK_1203 0x00021874
316 #define ARCMSR_DRV2IOP_DOORBELL_1203 0x00021878 /* window of "instruction flags" from…
317 #define ARCMSR_DRV2IOP_DOORBELL_MASK_1203 0x0002187C
320 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 /* ioctl transfer */
321 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 /* ioctl transfer */
322 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004
323 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
325 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F
326 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0
327 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7
329 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2I…
330 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2I…
331 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP…
332 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP…
333 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16…
334 #define ARCMSR_MESSAGE_START_BGRB 0x00060008 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2I…
335 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008
336 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008
337 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008
338 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */
340 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 /* ioctl transfer */
341 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 /* ioctl transfer */
342 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004
343 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008
344 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 /* */
347 #define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 /* iop msgcode_rwbuffer for message command */
348 #define ARCMSR_IOCTL_WBUFFER 0x0000fe00 /* user space data to iop 128bytes */
349 #define ARCMSR_IOCTL_RBUFFER 0x0000ff00 /* iop data to user space 128bytes */
350 #define ARCMSR_HBB_BASE0_OFFSET 0x00000010
351 #define ARCMSR_HBB_BASE1_OFFSET 0x00000018
352 #define ARCMSR_HBB_BASE0_LEN 0x00021000
353 #define ARCMSR_HBB_BASE1_LEN 0x00010000
362 #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A int…
363 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbo…
364 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post…
365 #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */
367 #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001
372 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004
379 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
385 #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010
391 #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002/**/
392 #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004/**/
393 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008/*inbound message 0 ready…
394 #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010/*more than 12 request co…
395 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002/**/
396 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002/*outbound DATA WRITE isr…
397 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004/**/
398 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004/*outbound DATA READ isr …
399 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008/*outbound message 0 read…
400 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008/*outbound message cmd is…
401 #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/
402 #define ARCMSR_HBCMU_RESET_ADAPTER 0x00000024
403 #define ARCMSR_HBCMU_DiagWrite_ENABLE 0x00000080
410 #define ARCMSR_HBDMU_CHIP_ID 0x00004
411 #define ARCMSR_HBDMU_CPU_MEMORY_CONFIGURATION 0x00008
412 #define ARCMSR_HBDMU_I2_HOST_INTERRUPT_MASK 0x00034
413 #define ARCMSR_HBDMU_MAIN_INTERRUPT_STATUS 0x00200
414 #define ARCMSR_HBDMU_PCIE_F0_INTERRUPT_ENABLE 0x0020C
415 #define ARCMSR_HBDMU_INBOUND_MESSAGE0 0x00400
416 #define ARCMSR_HBDMU_INBOUND_MESSAGE1 0x00404
417 #define ARCMSR_HBDMU_OUTBOUND_MESSAGE0 0x00420
418 #define ARCMSR_HBDMU_OUTBOUND_MESSAGE1 0x00424
419 #define ARCMSR_HBDMU_INBOUND_DOORBELL 0x00460
420 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL 0x00480
421 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL_ENABLE 0x00484
422 #define ARCMSR_HBDMU_INBOUND_LIST_BASE_LOW 0x01000
423 #define ARCMSR_HBDMU_INBOUND_LIST_BASE_HIGH 0x01004
424 #define ARCMSR_HBDMU_INBOUND_LIST_WRITE_POINTER 0x01018
425 #define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_LOW 0x01060
426 #define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_HIGH 0x01064
427 #define ARCMSR_HBDMU_OUTBOUND_LIST_COPY_POINTER 0x0106C
428 #define ARCMSR_HBDMU_OUTBOUND_LIST_READ_POINTER 0x01070
429 #define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_CAUSE 0x01088
430 #define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_ENABLE 0x0108C
432 #define ARCMSR_HBDMU_MESSAGE_WBUFFER 0x02000
433 #define ARCMSR_HBDMU_MESSAGE_RBUFFER 0x02100
434 #define ARCMSR_HBDMU_MESSAGE_RWBUFFER 0x02200
440 #define ARCMSR_HBDMU_ALL_INT_ENABLE 0x00001010 /* enable all ISR */
441 #define ARCMSR_HBDMU_ALL_INT_DISABLE 0x00000000 /* disable all ISR */
444 #define ARCMSR_HBDMU_OUTBOUND_INT 0x00001010
445 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT 0x00001000
446 #define ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT 0x00000010
449 #define ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY 0x00000001
450 #define ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ 0x00000002
452 #define ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK 0x00000001
453 #define ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK 0x00000002
455 /*outbound message 0 ready*/
456 #define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE 0x02000000
458 #define ARCMSR_HBDMU_F0_DOORBELL_CAUSE 0x02000003
461 #define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR 0x02000000
464 #define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT 0x00000001
465 #define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001
468 #define ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK 0x80000000
474 #define ARCMSR_SIGNATURE_1884 0x188417D3
475 #define ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR 0x00000001
476 #define ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
477 #define ARCMSR_HBEMU_ALL_INTMASKENABLE 0x00000009 /* disable all ISR */
479 #define ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK 0x00000002
480 #define ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK 0x00000004
481 #define ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008 /* inbound message 0 ready */
482 #define ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 0x00000002
483 #define ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 0x00000004
484 #define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 /* outbound message 0 ready */
485 #define ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK */
487 #define ARCMSR_HBEMU_DOORBELL_SYNC 0x100
488 #define ARCMSR_ARC188X_RESET_ADAPTER 0x00000004
494 #define ARCMSR_SIGNATURE_1886 0x188617D3
497 #define ARCMSR_HBFMU_DOORBELL_SYNC 0x100
498 //set host rw buffer physical address at inbound message 0, 1 (low,high)
499 #define ARCMSR_HBFMU_DOORBELL_SYNC1 0x300
500 #define ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK 0x80000000
501 #define ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE 0x20000000
527 u_int32_t msgcode_rwbuffer[256]; /*0a00 0DFF 256*/
528 u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/
529 u_int32_t reserved5[32]; /*0E80 0EFF 32*/
530 u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/
531 u_int32_t reserved6[32]; /*0F80 0FFF 32*/
541 …u_int32_t iop2drv_doorbell; /*offset 0x00021870:00,01,02,03: window of "instruction flags…
549 …u_int32_t drv2iop_doorbell; /*offset 0x00020400:00,01,02,03: window of "instruction flags…
562 …u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message co…
563 …u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space…
565 …u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data t…
680 uint32_t chip_id; //0x0004
681 uint32_t cpu_mem_config; //0x0008
682 uint32_t reserved1[10]; //0x000C
683 uint32_t i2o_host_interrupt_mask; //0x0034
684 uint32_t reserved2[114]; //0x0038
685 uint32_t host_int_status; //0x0200
686 uint32_t host_int_enable; //0x0204
687 uint32_t reserved3[1]; //0x0208
688 uint32_t pcief0_int_enable; //0x020C
689 uint32_t reserved4[124]; //0x0210
690 uint32_t inbound_msgaddr0; //0x0400
691 uint32_t inbound_msgaddr1; //0x0404
692 uint32_t reserved5[6]; //0x0408
693 uint32_t outbound_msgaddr0; //0x0420
694 uint32_t outbound_msgaddr1; //0x0424
695 uint32_t reserved6[14]; //0x0428
696 uint32_t inbound_doorbell; //0x0460
697 uint32_t reserved7[7]; //0x0464
698 uint32_t outbound_doorbell; //0x0480
699 uint32_t outbound_doorbell_enable; //0x0484
700 uint32_t reserved8[734]; //0x0488
701 uint32_t inboundlist_base_low; //0x1000
702 uint32_t inboundlist_base_high; //0x1004
703 uint32_t reserved9[4]; //0x1008
704 uint32_t inboundlist_write_pointer; //0x1018
705 uint32_t inboundlist_read_pointer; //0x101C
706 uint32_t reserved10[16]; //0x1020
707 uint32_t outboundlist_base_low; //0x1060
708 uint32_t outboundlist_base_high; //0x1064
709 uint32_t reserved11; //0x1068
710 uint32_t outboundlist_copy_pointer; //0x106C
711 uint32_t outboundlist_read_pointer; //0x1070 0x1072
712 uint32_t reserved12[5]; //0x1074
713 uint32_t outboundlist_interrupt_cause; //0x1088
714 uint32_t outboundlist_interrupt_enable; //0x108C
715 uint32_t reserved13[988]; //0x1090
716 uint32_t message_wbuffer[32]; //0x2000
717 uint32_t reserved14[32]; //0x2080
718 uint32_t message_rbuffer[32]; //0x2100
719 uint32_t reserved15[32]; //0x2180
720 uint32_t msgcode_rwbuffer[256]; //0x2200
885 u_int16_t cmdLMID; // reserved (0)
886 u_int16_t cmdFlag2; // reserved (0)
912 #define IS_SG64_ADDR 0x01000000 /* bit24 */
919 ** 1. Message 0 --> InitThread message and retrun code
926 ** offset 0xf00 : for RS232 out (request buffer)
927 ** offset 0xe00 : for RS232 in (scratch buffer)
928 ** offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331)
929 ** offset 0xa00 : for outbound message code msgcode_rwbuffer (IOP331 send to driver)
939 ** bit31 : 0 : 256 bytes frame
941 ** bit30 : 0 : normal request
950 ** bit31 : must be 0 (for this type of reply)
953 ** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData
960 ** offset: 0x78 : Request Frame (bit30 == 1)
961 ** offset: 0x18 : writeonly to generate IRQ to IOP331
963 ** (bit30 == 0, bit28==err flag)
967 ** 0x00 : NOP
968 ** 0x01 : Get Config ->offset 0xa00 :for outbound message code msgcode_rwbuffer (IOP331 send to d…
969 ** Signature 0x87974060(4)
970 ** Request len 0x00000200(4)
971 ** numbers of queue 0x00000100(4)
972 ** SDRAM Size 0x00000100(4)-->256 MB
973 ** IDE Channels 0x00000008(4)
980 ** 0x02 : Set Config ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to I…
981 ** Signature 0x87974063(4)
983 ** 0x03 : Reset (Abort all queued Command)
984 ** 0x04 : Stop Background Activity
985 ** 0x05 : Flush Cache
986 ** 0x06 : Start Background Activity (re-start if background is halted)
987 ** 0x07 : Check If Host Command Pending (Novell May Need This Function)
988 ** 0x08 : Set controller time ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver …
989 ** byte 0 : 0xaa <-- signature
990 ** byte 1 : 0x55 <-- signature
994 ** byte 5 : hour (0..23)
995 ** byte 6 : minute (0..59)
996 ** byte 7 : second (0..59)
1000 ** <1> Message Register 0,1 (the same usage) Init Thread message and retrun code
1001 ** Inbound Message 0 (inbound_msgaddr0) : at offset 0xB0 (Scratchpad0) for inbound messa…
1002 ** Inbound Message 1 (inbound_msgaddr1) : at offset 0xB4 (Scratchpad1) Out.... Diag Stat…
1003 ** Outbound Message 0 (outbound_msgaddr0): at offset 0xB8 (Scratchpad3) Out.... Diag Stat…
1004 ** Outbound Message 1 (outbound_msgaddr1): at offset 0xBC (Scratchpad2) for outbound mess…
1007 ** inbound doorbell: bit3 -- inbound message 0 ready (driver to iop)
1008 ** outbound doorbell: bit3 -- outbound message 0 ready (iop to driver)
1013 ** 0x00 : NOP
1014 ** 0x01 : Get Config ->offset 0xB8 :for outbound message code msgcode_rwbuffer (IOP s…
1015 ** Signature 0x87974060(4)
1016 ** Request len 0x00000200(4)
1017 ** numbers of queue 0x00000100(4)
1018 ** SDRAM Size 0x00000100(4)-->256 MB
1019 ** IDE Channels 0x00000008(4)
1025 ** 0x02 : Set Config ->offset 0xB0 :for inbound message code msgcode_rwbuffer (driver…
1026 ** Signature 0x87974063(4)
1028 ** 0x03 : Reset (Abort all queued Command)
1029 ** 0x04 : Stop Background Activity
1030 ** 0x05 : Flush Cache
1031 ** 0x06 : Start Background Activity (re-start if background is halted)
1032 ** 0x07 : Check If Host Command Pending (Novell May Need This Function)
1033 ** 0x08 : Set controller time ->offset 0xB0 : for inbound message code msgcode_rwbuff…
1034 ** byte 0 : 0xaa <-- signature
1035 ** byte 1 : 0x55 <-- signature
1039 ** byte 5 : hour (0..23)
1040 ** byte 6 : minute (0..59)
1041 ** byte 7 : second (0..59)
1047 ** inbound doorbell : at offset 0x20
1048 ** inbound doorbell clear : at offset 0x70
1053 ** bit3 -- inbound message 0 ready
1056 ** outbound doorbell : at offset 0x9C
1057 ** outbound doorbell clear : at offset 0xA0
1062 ** bit3 -- outbound message 0 ready
1065 ** COMPORT_IN at 0x2000: message_wbuffer -- 128 bytes (to be sent to ROC) : for RS…
1066 ** COMPORT_OUT at 0x2100: message_rbuffer -- 128 bytes (to be sent to host): for RS…
1067 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for outbound message code ms…
1068 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for inbound message code ms…
1072 ** inbound queue port32 at offset 0x40 , 0x41, 0x42, 0x43
1073 ** inbound queue port64 at offset 0xC0 (lower)/0xC4 (upper)
1074 ** outbound queue port32 at offset 0x44
1075 ** outbound queue port64 at offset 0xC8 (lower)/0xCC (upper)
1077 ** i.e. write 0x40/0xC0, ROC will get the request with high part == 0, the
1084 ** then low part, to check queue empty, ONLY check high part to be 0xFFFFFFFF.
1085 ** If high part is 0xFFFFFFFF, DO NOT read low part, this may corrupt the
1087 ** at 0x30 bit3.
1096 ** 000: <= 0x0080 (128)
1097 ** 001: <= 0x0100 (256)
1098 ** 010: <= 0x0180 (384)
1099 ** 011: <= 0x0200 (512)
1100 ** 100: <= 0x0280 (640)
1101 ** 101: <= 0x0300 (768)
1102 ** 110: <= 0x0300 (reserved)
1103 ** 111: <= 0x0300 (reserved)
1105 ** if len > 0x300 the len always set as 0x300
1115 ** bit0:0 , no error, 1 with error, refer to status buffer
1116 ** bit1:0 , reserved (will be 0)
1117 ** bit2:0 , reserved (will be 0)
1118 ** bit3:0 , reserved (will be 0)
1134 struct SG32ENTRY { /* length bit 24 == 0 */
1179 u_int32_t signature; /*0,00-03*/
1193 ** if low BYTE (byte#0) >= 3 (version 3)
1197 ** 0 256K
1206 ** large CDB block in 0x100 unit (we use 0x100 byte as one page)
1207 ** e.g. If the length of CDB including MSG header and SGL is 0x1508
1208 ** driver need to set the msgPages to 0x16
1211 ** <= 0x100 1 0
1212 ** <= 0x200 2 1
1213 ** <= 0x300 3 1
1214 ** <= 0x400 4 1
1221 ** size 0x1F8 (504)
1225 u_int8_t Bus; /* 00h should be 0 */
1226 u_int8_t TargetID; /* 01h should be 0--15 */
1227 u_int8_t LUN; /* 02h should be 0--7 */
1236 u_int32_t DataLength; /* 0ch not used now */
1255 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */
1256 #define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */
1257 #define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */
1258 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */
1259 #define ARCMSR_CDB_FLAG_HEADQ 0x08
1260 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10
1262 #define SCSISTAT_GOOD 0x00
1263 #define SCSISTAT_CHECK_CONDITION 0x02
1264 #define SCSISTAT_CONDITION_MET 0x04
1265 #define SCSISTAT_BUSY 0x08
1266 #define SCSISTAT_INTERMEDIATE 0x10
1267 #define SCSISTAT_INTERMEDIATE_COND_MET 0x14
1268 #define SCSISTAT_RESERVATION_CONFLICT 0x18
1269 #define SCSISTAT_COMMAND_TERMINATED 0x22
1270 #define SCSISTAT_QUEUE_FULL 0x28
1272 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0
1273 #define ARCMSR_DEV_ABORTED 0xF1
1274 #define ARCMSR_DEV_INIT_FAIL 0xF2
1278 ** SRB must be not cross page boundary,and the order from offset 0
1284 …struct ARCMSR_CDB arcmsr_cdb; /* 0 -503 (size of CDB=504): arcmsr messenger scsi command descrip…
1298 #define SRB_FLAG_READ 0x0000
1299 #define SRB_FLAG_WRITE 0x0001
1300 #define SRB_FLAG_ERROR 0x0002
1301 #define SRB_FLAG_FLUSHCACHE 0x0004
1302 #define SRB_FLAG_MASTER_ABORTED 0x0008
1303 #define SRB_FLAG_DMAVALID 0x0010
1304 #define SRB_FLAG_DMACONSISTENT 0x0020
1305 #define SRB_FLAG_DMAWRITE 0x0040
1306 #define SRB_FLAG_PKTBIND 0x0080
1307 #define SRB_FLAG_TIMER_START 0x0080
1308 #define SRB_FLAG_DIRECT_IO 0x0100
1309 #define SRB_FLAG_USE_SG 0x0200
1311 #define ARCMSR_SRB_DONE 0x0000
1312 #define ARCMSR_SRB_UNBUILD 0x0000
1313 #define ARCMSR_SRB_TIMEOUT 0x1111
1314 #define ARCMSR_SRB_RETRY 0x2222
1315 #define ARCMSR_SRB_START 0x55AA
1316 #define ARCMSR_SRB_PENDING 0xAA55
1317 #define ARCMSR_SRB_RESET 0xA5A5
1318 #define ARCMSR_SRB_ABORTED 0x5A5A
1319 #define ARCMSR_SRB_ILLEGAL 0xFFFF
1321 #define SRB_SIZE ((sizeof(struct CommandControlBlock)+0x1f) & 0xffe0)
1329 #define ACB_ADAPTER_TYPE_A 0x00000000 /* hba I IOP */
1330 #define ACB_ADAPTER_TYPE_B 0x00000001 /* hbb M IOP */
1331 #define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */
1332 #define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */
1333 #define ACB_ADAPTER_TYPE_E 0x00000004 /* hbd L IOP */
1334 #define ACB_ADAPTER_TYPE_F 0x00000005 /* hbd L IOP */
1373 uint32_t *message_wbuffer; //0x000 - COMPORT_IN (to be sent to ROC)
1374 uint32_t *message_rbuffer; //0x100 - COMPORT_OUT (to be sent to Host)
1375 uint32_t *msgcode_rwbuffer; //0x200 - BIOS_AREA
1442 …ize; // total buffer size(must be multiples of MB, this version should be 128+3 MB, i.e. 0x8300000)
1443 u_int32_t hrbRes[2]; // reserved, must be set to 0
1454 #define ACB_F_SCSISTOPADAPTER 0x0001
1455 #define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */
1456 #define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */
1457 #define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */
1458 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */
1459 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */
1460 #define ACB_F_MESSAGE_WQBUFFER_READ 0x0040
1461 #define ACB_F_BUS_RESET 0x0080
1462 #define ACB_F_IOP_INITED 0x0100 /* iop init */
1463 #define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb failed */
1464 #define ACB_F_CAM_DEV_QFRZN 0x0400
1465 #define ACB_F_BUS_HANG_ON 0x0800 /* need hardware reset bus */
1466 #define ACB_F_SRB_FUNCTION_POWER 0x1000
1467 #define ACB_F_MSIX_ENABLED 0x2000
1468 #define ACB_F_MSG_GET_CONFIG 0x4000
1469 #define ACB_F_DIRECT_IO 0x8000
1470 #define ACB_F_DMAMAP_SRB 0x10000
1471 #define ACB_F_DMAMAP_SGTABLE 0x20000
1472 #define ACB_F_DMAMAP_SG 0x40000
1473 #define ACB_F_MAPXOR_FAILD 0x80000
1475 #define ARECA_RAID_GONE 0x55
1476 #define ARECA_RAID_GOOD 0xaa
1478 #define ACB_BUS_SPEED_3G 0
1507 #define SCSI_DASD 0x00 /* Direct-access Device */
1508 #define SCSI_SEQACESS 0x01 /* Sequential-access device */
1509 #define SCSI_PRINTER 0x02 /* Printer device */
1510 #define SCSI_PROCESSOR 0x03 /* Processor device */
1511 #define SCSI_WRITEONCE 0x04 /* Write-once device */
1512 #define SCSI_CDROM 0x05 /* CD-ROM device */
1513 #define SCSI_SCANNER 0x06 /* Scanner device */
1514 #define SCSI_OPTICAL 0x07 /* Optical memory device */
1515 #define SCSI_MEDCHGR 0x08 /* Medium changer device */
1516 #define SCSI_COMM 0x09 /* Communications device */
1517 #define SCSI_NODEV 0x1F /* Unknown or no device type */
1541 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 …
1549 …reserved | Header Type | Primary MLT | Primary CLS | 0Ch
1578 ** 0x03-0x00 :
1585 #define ARCMSR_PCI2PCI_VENDORID_REG 0x00 /*word*/
1586 #define ARCMSR_PCI2PCI_DEVICEID_REG 0x02 /*word*/
1589 ** 0x05-0x04 : command register
1592 ** 10 0 Interrupt Disable: Disables/Enables the generation of Interrupts …
1594 ** 09 0 FB2B Enable: Enables/Disables the generation of fast back t…
1598 ** 08 0 SERR# Enable (SEE): Enables primary bus SERR# assertions.
1599 ** 0=The bridge does not assert P_SERR#.
1601 ** 07 0 Wait Cycle Control (WCC): Always returns 0bzero indicating
1603 ** 06 0 Parity Error Response (PER): Controls bridge response to a detected primary…
1604 ** 0=When a data parity error is detected bridg…
1611 ** 05 0 VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible …
1613 ** whose address bits are: P_AD[9:0] equal to 3C6h, 3C8h or 3C9h
1616 ** (i.e., must be all 0's depending upon the VGA
1619 ** 0=The bridge ignores VGA palette write tr…
1623 ** 04 0 Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transa…
1626 ** 03 0 Special Cycle Enable (SCE): The bridge ignores special cycle tran…
1627 … This bit is read only and always returns 0 when read
1628 ** 02 0 Bus Master Enable (BME): Enables bridge to initiate memory and…
1630 ** 0=The bridge does not initiate memory…
1632 ** 01 0 Memory Space Enable (MSE): Controls target response to memory tr…
1633 ** 0=The bridge target response to memor…
1635 ** 00 0 I/O Space Enable (IOSE): Controls target response to I/O trans…
1636 ** 0=The bridge target response to I/O t…
1640 #define ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG 0x04 /*word*/
1641 #define PCI_DISABLE_INTERRUPT 0x0400
1644 ** 0x07-0x06 : status register
1646 ** 15 0 Detected Parity Error: The bridge sets this bit to a 1b when…
1649 ** 14 0 Signaled System Error: The bridge sets this bit to a 1b when…
1650 ** 13 0 Received Master Abort: The bridge sets this bit to a 1b when…
1654 ** 12 0 Received Target Abort: The bridge sets this bit to a 1b when…
1657 ** 11 0 Signaled Target Abort: The bridge sets this bit to a 1b when…
1662 ** 08 0 Master Data Parity Error: The bridge sets this bit to a 1b when…
1668 ** 06 0 Reserved
1675 ** 03 0 Interrupt Status: Reflects the state of the interrupt i…
1680 #define ARCMSR_PCI2PCI_PRIMARY_STATUS_REG 0x06 /*word: 06,07 */
1681 #define ARCMSR_ADAP_66MHZ 0x20
1684 ** 0x08 : revision ID
1686 ** 07:00 00000000 Revision ID (RID): '00h' indicating bridge A-0 stepping.
1689 #define ARCMSR_PCI2PCI_REVISIONID_REG 0x08 /*byte*/
1692 ** 0x0b-0x09 : 0180_00 (class code 1,native pci mode )
1699 #define ARCMSR_PCI2PCI_CLASSCODE_REG 0x09 /*3bytes*/
1702 ** 0x0c : cache line size
1713 #define ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C /*byte*/
1716 ** 0x0d : latency timer (number of pci clock 00-ff )
1737 #define ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG 0x0D /*byte*/
1740 ** 0x0e : (header type,single function )
1742 ** 07 0 Multi-function device (MVD): 80331 is a single-function device.
1748 #define ARCMSR_PCI2PCI_HEADERTYPE_REG 0x0E /*byte*/
1751 ** 0x0f :
1756 ** 0x13-0x10 :
1757 ** PCI CFG Base Address #0 (0x10)
1762 ** 0x17-0x14 :
1763 ** PCI CFG Base Address #1 (0x14)
1768 ** 0x1b-0x18 :
1769 ** PCI CFG Base Address #2 (0x18)
1770 **-----------------0x1A,0x19,0x18--Bus Number Register - BNR
1779 ** is translated to a Type 0 configuration cycle (or a Special Cycle)
1785 **-----------------0x1B--Secondary Latency Timer Register - SLTR
1807 #define ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG 0x18 /*3byte 0x1A,0x19,0x18*/
1808 #define ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG 0x19 /*byte*/
1809 #define ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG 0x1A /*byte*/
1810 #define ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG 0x1B /*byte*/
1813 ** 0x1f-0x1c :
1814 ** PCI CFG Base Address #3 (0x1C)
1815 **-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL
1817 ** 15:12 0h I/O Limit Address Bits [15:12]: Defines the top address of an address…
1820 ** Bits 11:0 are assumed to be FFFh.
1822 ** 07:04 0h I/O Base Address Bits [15:12]: Defines the bottom address of
1826 ** Bits 11:0 are assumed to be 000h.
1828 **-----------------0x1F,0x1E--Secondary Status Register - SSR
1830 ** 15 0b Detected Parity Error: The bridge sets this bit to a 1b when…
1832 ** 14 0b Received System Error: The bridge sets this bit when it samp…
1833 ** 13 0b Received Master Abort: The bridge sets this bit to a 1b when…
1837 ** 12 0b Received Target Abort: The bridge sets this bit to a 1b when…
1840 ** 11 0b Signaled Target Abort: The bridge sets this bit to a 1b when…
1845 ** 08 0b Master Data Parity Error: The bridge sets this bit to a 1b when…
1850 ** 06 0b Reserved
1856 #define ARCMSR_PCI2PCI_IO_BASE_REG 0x1C /*byte*/
1857 #define ARCMSR_PCI2PCI_IO_LIMIT_REG 0x1D /*byte*/
1858 #define ARCMSR_PCI2PCI_SECONDARY_STATUS_REG 0x1E /*word: 0x1F,0x1E */
1861 ** 0x23-0x20 :
1862 ** PCI CFG Base Address #4 (0x20)
1863 **-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL
1868 … For the purposes of address decoding the lower 20 address bits (P_AD[19:0]
1870 ** 19:16 0h Reserved.
1875 … For the purposes of address decoding the lower 20 address bits (P_AD[19:0])
1876 ** are assumed to be 0 0000h.
1877 ** 03:00 0h Reserved.
1880 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG 0x20 /*word: 0x21,0x20 */
1881 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG 0x22 /*word: 0x23,0x22 */
1884 ** 0x27-0x24 :
1885 ** PCI CFG Base Address #5 (0x24)
1886 **-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL
1891 … For the purposes of address decoding the lower 20 address bits (P_AD[19:0]
1898 … For the purposes of address decoding the lower 20 address bits (P_AD[19:0])
1899 ** are assumed to be 0 0000h.
1903 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG 0x24 /*word: 0x25,0x24 */
1904 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG 0x26 /*word: 0x27,0x26 */
1907 ** 0x2b-0x28 :
1913 … ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG 0x28 /*dword: 0x2b,0x2a,0x29,0x28 */
1916 ** 0x2f-0x2c :
1922 … ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG 0x2C /*dword: 0x2f,0x2e,0x2d,0x2c */
1925 ** 0x33-0x30 :
1931 #define ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG 0x34 /*byte*/
1934 ** 0x3b-0x35 : reserved
1939 ** 0x3d-0x3c :
1946 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG 0x3C /*byte*/
1947 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG 0x3D /*byte*/
1950 ** 0x3f-0x3e :
1952 ** 15:12 0h Reserved
1953 ** 11 0b Discard Timer SERR# Enable: Controls the generation of SERR# on t…
1955 ** 0b=SERR# is not asserted.
1957 ** 10 0b Discard Timer Status (DTS): This bit is set to a '1b' when either…
1959 ** 09 0b Secondary Discard Timer (SDT): Sets the maximum number of PCI clock …
1967 ** 0b=The secondary master time-out coun…
1969 ** 08 0b Primary Discard Timer (PDT): Sets the maximum number of PCI clock …
1977 ** 0b=The primary master time-out counte…
1979 ** 07 0b Fast Back-to-Back Enable (FBE): The bridge does not initiate back to …
1980 ** 06 0b Secondary Bus Reset (SBR):
1981 ** When cleared to 0b: The bridge deasse…
1984 ** 05 0b Master Abort Mode (MAM): Dictates bridge behavior on the initi…
1987 ** 0b=The bridge asserts TRDY# in respon…
1997 ** 04 0b VGA Alias Filter Enable: This bit dictates bridge behavior in …
2002 ** 0b=Ignores address bits AD[15:10] whe…
2004 …en all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b),
2006 ** 03 0b VGA Enable: Setting this bit enables address deco…
2015 ** 02 0b ISA Enable: Setting this bit enables special hand…
2020 ** 0b=All I/O transactions that fall wit…
2028 ** 01 0b SERR# Forward Enable: 0b=The bridge does not assert P_SERR#…
2031 ** 00 0b Parity Error Response: This bit controls bridge response to …
2033 ** 0b=When a data parity error is detect…
2042 #define ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG 0x3E /*word*/
2048 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 …
2050 ** | Bridge Control 0 | Arbiter Control/Status | Reserved …
2072 ** 0x42-0x41: Secondary Arbiter Control/Status Register - SACSR
2081 ** 0000b REQ#/GNT#[0]
2088 ** 11 0b Grant Time-out Occurred: When set to 1b,
2091 ** 10 0b Bus Parking Control: 0=During bus idle, bridge parks the b…
2098 ** or to the low priority arbiter ring (0b).
2099 … Bits [3:0] correspond to request inputs S_REQ#[3:0]…
2103 ** 0b=Indicates that the maste…
2106 ** 0x43: Bridge Control Register 0 - BCR0
2108 ** 07 0b Fully Dynamic Queue Mode: 0=The number of Posted write transact…
2112 ** 06:03 0H Reserved.
2113 ** 02 0b Upstream Prefetch Disable: This bit disables bridge ability
2119 ** 0b=bridge treats all upstream Memory Read requests as though the…
2131 ** 0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2)
2140 ** 0 0 Re-map to Memory Read/Write Block bef…
2141 ** 0 1 Enqueue and forward the alias command…
2142 ** 1 0 Ignore the transaction, forcing Maste…
2150 ** 0b=All 2 24 watchdog timers are enabl…
2155 ** 04 0b GRANT# time-out disable: This bit enables/disables the GNT# ti…
2157 ** 0b=The Secondary bus arbiter times ou…
2165 ** 02 0b Secondary Discard Timer Disable: This bit enables/disables bridge seco…
2169 ** 0b=The secondary master time-out coun…
2175 ** 01 0b Primary Discard Timer Disable: This bit enables/disables bridge prim…
2179 ** 0b=The primary master time-out counte…
2184 ** 00 0b Reserved
2186 ** 0x47-0x46: Bridge Control Register 2 - BCR2
2189 ** 06 0b Global Clock Out Disable (External Secondary Bus Clock Source Enable):
2199 … secondary PCI clock outputs. Some, or all secondary clock outputs (S_CLKO[3:0])
2203 ** all four S_CLKOs enabled by default. (SCLKO[3:0])�P
2206 ** (S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected
2209 ** 0x49-0x48: Bridge Status Register - BSR
2211 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and…
2213 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired:
2220 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired:
2226 ** 12 0b Master Abort during Upstream Posted Write: This bit is set to a 1b and…
2229 ** 11 0b Target Abort during Upstream Posted Write: This bit is set to a 1b and…
2232 ** 10 0b Upstream Posted Write Data Discarded: This bit is set to a 1b and…
2235 ** 09 0b Upstream Posted Write Data Parity Error: This bit is set to a 1b and…
2238 ** 08 0b Secondary Bus Address Parity Error: This bit is set to a 1b and…
2241 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b an…
2243 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired:
2251 ** 05 0b Downstream Delayed Write/Split Watchdog Timer Expired:
2259 ** 04 0b Master Abort during Downstream Posted Write: This bit is set to a 1b an…
2262 ** 03 0b Target Abort during Downstream Posted Write: This bit is set to a 1b an…
2265 ** 02 0b Downstream Posted Write Data Discarded: This bit is set to a 1b an…
2268 ** 01 0b Downstream Posted Write Data Parity Error: This bit is set to a 1b an…
2271 ** 00 0b Primary Bus Address Parity Error: This bit is set to a 1b an…
2274 ** 0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR
2297 ** When a given bit is cleared to 0b, its correspo…
2299 ** 0x53-0x52: Read Prefetch Policy Register - RPPR
2326 … Bit(3) is a ganged enable bit for REQ#/GNT#[7:3], and bits(2:0) provide individual
2327 … enable bits for REQ#/GNT#[2:0].
2330 ** 0b: disables staged p…
2343 ** 0x55-0x54: P_SERR# Assertion Control - SERR_CTL
2345 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavi…
2347 ** 0b=bridge asserts P_SERR#.
2349 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior f…
2350 ** 0b=bridge asserts P_SERR#.
2352 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior …
2353 ** 0b=bridge asserts P_SERR#.
2355 ** 12 0b Master Abort during Upstream Posted Write: Dictates bridge behavior …
2357 ** 0b=bridge asserts P_SERR#.
2359 ** 11 0b Target Abort during Upstream Posted Write: Dictates bridge behavior …
2361 ** 0b=bridge asserts P_SERR#.
2363 ** 10 0b Upstream Posted Write Data Discarded: Dictates bridge behavior …
2365 ** 0b=bridge asserts P_SERR#.
2367 ** 09 0b Upstream Posted Write Data Parity Error: Dictates bridge behavior
2369 ** 0b=bridge asserts P_SERR#.
2371 ** 08 0b Secondary Bus Address Parity Error: This bit dictates bridge …
2373 ** 0b=bridge asserts P_SERR#.
2375 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior …
2377 ** 0b=bridge asserts P_SERR#.
2379 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior …
2380 ** 0b=bridge asserts P_SERR#.
2382 ** 05 0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior …
2383 ** 0b=bridge asserts P_SERR#.
2385 ** 04 0b Master Abort during Downstream Posted Write: Dictates bridge behavior …
2387 ** 0b=bridge asserts P_SERR#.
2389 ** 03 0b Target Abort during Downstream Posted Write: Dictates bridge behavior …
2391 ** 0b=bridge asserts P_SERR#.
2393 ** 02 0b Downstream Posted Write Data Discarded: Dictates bridge behavior …
2395 ** 0b=bridge asserts P_SERR#.
2397 ** 01 0b Downstream Posted Write Data Parity Error: Dictates bridge behavior
2399 ** 0b=bridge asserts P_SERR#.
2401 ** 00 0b Primary Bus Address Parity Error: This bit dictates bridge …
2403 ** 0b=bridge asserts P_SERR#.
2406 ** 0x56: Pre-Boot Status Register - PBSR
2410 ** 05:02 0 Reserved
2416 ** ** 0 100 MHz
2418 ** 00 0b Reserved
2420 ** 0x59-0x58: Secondary Decode Enable Register - SDER
2430 ** 0x5D-0x5C: Secondary IDSEL Select Register - SISR
2434 ** AD25 is deasserted for any possible Type 1 to Type 0 conversion.
2436 ** AD25 is asserted when Primary addresses AD[15:11]=01001 2 during a Type 1 to Type 0 conver…
2438 ** AD24 is deasserted for any possible Type 1 to Type 0 conversion.
2440 ** AD24 is asserted when Primary addresses AD[15:11]=01000 2 during a Type 1 to Type 0 conver…
2442 ** AD23 is deasserted for any possible Type 1 to Type 0 conversion.
2444 ** AD23 is asserted when Primary addresses AD[15:11]=00111 2 during a Type 1 to Type 0 conver…
2446 ** AD22 is deasserted for any possible Type 1 to Type 0 conversion.
2448 ** AD22 is asserted when Primary addresses AD[15:11]=00110 2 during a Type 1 to Type 0 conver…
2450 ** AD21 is deasserted for any possible Type 1 to Type 0 conversion.
2452 ** AD21 is asserted when Primary addresses AD[15:11]=00101 2 during a Type 1 to Type 0 conver…
2454 ** AD20 is deasserted for any possible Type 1 to Type 0 conversion.
2456 ** AD20 is asserted when Primary addresses AD[15:11]=00100 2 during a Type 1 to Type 0 conver…
2458 ** AD19 is deasserted for any possible Type 1 to Type 0 conversion.
2460 ** AD19 is asserted when Primary addresses AD[15:11]=00011 2 during a Type 1 to Type 0 conver…
2462 ** AD18 is deasserted for any possible Type 1 to Type 0 conversion.
2464 ** AD18 is asserted when Primary addresses AD[15:11]=00010 2 during a Type 1 to Type 0 conver…
2466 ** AD17 is deasserted for any possible Type 1 to Type 0 conversion.
2468 ** AD17 is asserted when Primary addresses AD[15:11]=00001 2 during a Type 1 to Type 0 conver…
2470 ** AD16 is deasserted for any possible Type 1 to Type 0 conversion.
2472 ** AD16 is asserted when Primary addresses AD[15:11]=00000 2 during a Type 1 to Type 0 conver…
2485 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 …
2506 ** 0xDC: Power Management Capabilities Identifier - PM_CAPID
2510 ** 0xDD: Next Item Pointer - PM_NXTP
2514 ** 0xDF-0xDE: Power Management Capabilities Register - PMCR
2517 ** 10 0h State D2 Supported (D2): Indicates no support for state D2. No p…
2519 ** 08:06 0h Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux au…
2521 ** 05 0 Special Initialization Required (SINT): Special initialization is not required …
2525 ** 0xE1-0xE0: Power Management Control / Status - Register - PMCSR
2528 ** 08 0b PME_Enable: This bit, when set to 1b enables bridge to a…
2538 ** 0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE
2540 ** 07 0 Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clo…
2541 ** 06 0 B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines…
2546 ** 0xE3: Power Management Data Register - PMDR
2550 ** 0xF0: PCI-X Capabilities Identifier - PX_CAPID
2554 ** 0xF1: Next Item Pointer - PX_NXTP
2559 ** 0xF3-0xF2: PCI-X Secondary Status - PX_SSTS
2571 ** 05 0b Split Request Delayed. (SRD): This bit is supposed to be set …
2575 ** 04 0b Split Completion Overrun (SCO): This bit is supposed to be set w…
2577 ** 03 0b Unexpected Split Completion (USC): This bit is set when an unexpect…
2579 ** and function number 0 is received on the secondary interface.
2581 ** 02 0b Split Completion Discarded (SCD): This bit is set
2587 ** 0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS
2589 ** 31:22 0 Reserved
2590 ** 21 0 Split Request Delayed (SRD): This bit does not be set by bridge.
2591 ** 20 0 Split Completion Overrun (SCO): This bit does not be set by bridge
2593 ** 19 0 Unexpected Split Completion (USC): The bridge sets this bit to 1b
2596 ** 18 0 Split Completion Discarded (SCD): The bridge sets this bit to 1b
2599 ** 0=The maximum operating frequency is 66 MHz.
2602 ** 0=Primary Interface is connected as a 32-bit PCI bus.
2610 ** 02:00 0h Function Number (FNUM): The br…
2612 ** 0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC
2625 ** 0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC
2645 ** The ATU is programmed via a [Type 0] configuration command on the PCI interface.
2647 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 …
2655 … ATUBISTR | Header Type | Latency Timer | Cacheline Size | 0CH
2657 ** | Inbound ATU Base Address 0 …
2659 ** | Inbound ATU Upper Base Address 0 …
2688 ** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Inte…
2694 #define ARCMSR_ATU_VENDOR_ID_REG 0x00 /*word*/
2700 ** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the …
2704 #define ARCMSR_ATU_DEVICE_ID_REG 0x02 /*word*/
2711 ** 10 0 Interrupt Disable - This bit disables 80331 from assert…
2712 ** 0=enables the assertion of interrup…
2714 ** 09 0 2 Fast Back to Back Enable - When cleared,
2717 ** 08 0 2 SERR# Enable - When cleared, the ATU interface is not a…
2721 ** 06 0 2 Parity Error Response - When set, the ATU takes normal …
2723 ** 05 0 2 VGA Palette Snoop Enable - The ATU interface does not s…
2725 ** 04 0 2 Memory Write and Invalidate Enable - When set, ATU may …
2727 ** 03 0 2 Special Cycle Enable - The ATU interface does not respo…
2729 ** 02 0 2 Bus Master Enable - The ATU interface can act as a mast…
2734 ** 01 0 2 Memory Enable - Controls the ATU interface��s response …
2736 ** 00 0 2 I/O Space Enable - Controls the ATU interface response …
2740 #define ARCMSR_ATU_COMMAND_REG 0x04 /*word*/
2746 ** 15 0 2 Detected Parity Error - set when a parity error is dete…
2751 ** 14 0 2 SERR# Asserted - set when SERR# is asserted on the PCI …
2752 ** 13 0 2 Master Abort - set when a transaction initiated by the …
2754 ** 12 0 2 Target Abort (master) - set when a transaction initiate…
2756 ** 11 0 2 Target Abort (target) - set when the ATU interface, act…
2766 ** 08 0 2 Master Parity Error - The ATU interface sets this bit u…
2774 ** 0 2 (PCI-X mode)
2777 ** back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI…
2778 ** 06 0 2 UDF Supported - User Definable Features are not support…
2781 ** 03 0 Interrupt Status - reflects the state of the ATU interr…
2782 ** when the Interrupt Disable bit in the command register is a 0.
2783 ** 0=ATU interrupt signal deasserted.
2791 #define ARCMSR_ATU_STATUS_REG 0x06 /*word*/
2800 #define ARCMSR_ATU_REVISION_REG 0x08 /*byte*/
2811 #define ARCMSR_ATU_CLASS_CODE_REG 0x09 /*3bytes 0x0B,0x0A,0x09*/
2817 …fies the system cacheline size in DWORDs. Cacheline size is restricted to either 0, 8 or 16 DWORDs.
2820 #define ARCMSR_ATU_CACHELINE_SIZE_REG 0x0C /*byte*/
2828 ** Programmable Latency Timer - This field varies the latency timer for the interface from 0 to…
2829 ** The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode.
2833 #define ARCMSR_ATU_LATENCY_TIMER_REG 0x0D /*byte*/
2839 ** 07 0 2 Single Function/Multi-Function Device - Identifies the …
2844 #define ARCMSR_ATU_HEADER_TYPE_REG 0x0E /*byte*/
2854 ** 07 0 2 BIST Capable - This bit value is always equal to the AT…
2855 ** 06 0 2 Start BIST - When the ATUCR BIST Interrupt Enable bit i…
2858 ** found in ATUBISTR register bits [3:0].
2868 #define ARCMSR_ATU_BIST_REG 0x0F /*byte*/
2875 …und ATU Base Address Register 0 Inbound ATU Limit Register 0 Defines the inbo…
2876 …gister 0 N/A Together with ATU Base Address Register 0 def…
2895 ** Inbound ATU Base Address Register 0 - IABAR0
2897 … . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Addre…
2898 ** defines the block of memory addresses where the inbound translation window 0 begins.
2901 ** . Bits 31 through 12 of the IABAR0 is either read/write bits or read only with a value of 0
2919 ** 31:12 00000H Translation Base Address 0 - These bits define the actu…
2926 ** 00 0 2 Memory Space Indicator - This bit field describes memor…
2931 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG 0x10 /*dword 0x13,0x12,0x11,0x10*/
2932 #define ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE 0x08
2933 #define ARCMSR_INBOUND_ATU_MEMORY_WINDOW64 0x04
2936 ** Inbound ATU Upper Base Address Register 0 - IAUBAR0
2947 ** 31:0 00000H Translation Upper Base Address 0 - Together with the Tr…
2951 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG 0x14 /*dword 0x17,0x16,0x15,0x14*/
2978 ** 03 0 2 Prefetchable Indicator - When set, defines the memory s…
2982 ** 00 0 2 Memory Space Indicator - This bit field describes memor…
2987 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG 0x18 /*dword 0x1B,0x1A,0x19,0x18*/
3005 ** 31:0 00000H Translation Upper Base Address 1 - Together with the Tr…
3009 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG 0x1C /*dword 0x1F,0x1E,0x1D,0x1…
3018 ** . Bits 31 through 12 of the IABAR2 is either read/write bits or read only with a value of 0 dep…
3039 ** 03 0 2 Prefetchable Indicator - When set, defines the memory s…
3043 ** 00 0 2 Memory Space Indicator - This bit field describes memor…
3048 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/
3064 ** 31:0 00000H Translation Upper Base Address 2 - Together with the Tr…
3069 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG 0x24 /*dword 0x27,0x26,0x25,0x2…
3075 ** 15:0 0000H Subsystem Vendor ID - This register uniquely identifies…
3078 #define ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG 0x2C /*word 0x2D,0x2C*/
3084 ** 15:0 0000H Subsystem ID - uniquely identifies the add-in board or …
3087 #define ARCMSR_ATU_SUBSYSTEM_ID_REG 0x2E /*word 0x2F,0x2E*/
3096 ** 00 0 2 Address Decode Enable - This bit field shows the ROM ad…
3100 #define ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG 0x30 /*dword 0x33,0x32,0v31,0x30*/
3101 #define ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE 0x01
3111 #define ARCMSR_ATU_CAPABILITY_PTR_REG 0x34 /*byte*/
3121 ** As an example, assume that FFFF.FFFFH is written to the ATU Inbound Base Address Register 0
3128 ** which bits are read only (0). This allows the programming of these registers in a manner simila…
3177 #define ARCMSR_ATU_INTERRUPT_LINE_REG 0x3C /*byte*/
3186 #define ARCMSR_ATU_INTERRUPT_PIN_REG 0x3D /*byte*/
3195 #define ARCMSR_ATU_MINIMUM_GRANT_REG 0x3E /*byte*/
3205 #define ARCMSR_ATU_MAXIMUM_LATENCY_REG 0x3F /*byte*/
3220 ** The ATU uses the following registers in inbound address window 0 translation:
3221 ** �E Inbound ATU Base Address Register 0
3222 ** �E Inbound ATU Limit Register 0
3223 ** �E Inbound ATU Translate Value Register 0
3246 ** When (PCI_Address [31:0] & Limit_Register[31:0]) == (Base_Register[31:0] & PCI_Addr…
3254 ** Note: The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for …
3262 …ocessor Internal Bus Address=(PCI_Address[31:0] & ~Limit_Register[31:0]) | ATU_Translate_Value_Reg…
3295 ** Inbound ATU Limit Register 0 - IALR0
3297 ** Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI
3305 ** one to one correspondence. A value of 0 in a bit within the IALR0 makes the corresponding bit
3306 ** within the IABAR0 a read only bit which always returns 0. A value of 1 in a bit within the IALR0
3312 ** 31:12 FF000H Inbound Translation Limit 0 - This readback value deter…
3313 ** inbound memory window 0 of the address translation unit…
3317 #define ARCMSR_INBOUND_ATU_LIMIT0_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/
3320 ** Inbound ATU Translate Value Register 0 - IATVR0
3322 ** The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to
3327 ** 31:12 FF000H Inbound ATU Translation Value 0 - This value is used to…
3333 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/
3341 ** to one correspondence. A value of 0 in a bit within the ERLR makes the corresponding bit within
3342 ** the ERBAR a read only bit which always returns 0. A value of 1 in a bit within the ERLR makes
3347 … value is 0, which indicates no Expansion ROM address space and all bits within the ERB…
3351 #define ARCMSR_EXPANSION_ROM_LIMIT_REG 0x48 /*dword 0x4B,0x4A,0x49,0x48*/
3366 #define ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG 0x4C /*dword 0x4F,0x4E,0x4D,0x4C…
3372 ** one to one correspondence. A value of 0 in a bit within the IALR1 makes the corresponding bit
3373 ** within the IABAR1 a read only bit which always returns 0. A value of 1 in a bit within the IALR1
3389 #define ARCMSR_INBOUND_ATU_LIMIT1_REG 0x50 /*dword 0x53,0x52,0x51,0x50*/
3406 ** one to one correspondence. A value of 0 in a bit within the IALR2 makes the corresponding bit
3407 ** within the IABAR2 a read only bit which always returns 0. A value of 1 in a bit within the IALR2
3419 #define ARCMSR_INBOUND_ATU_LIMIT2_REG 0x54 /*dword 0x57,0x56,0x55,0x54*/
3435 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG 0x58 /*dword 0x5B,0x5A,0x59,0x58*/
3451 … ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG 0x5C /*dword 0x5F,0x5E,0x5D,0x5C*/
3454 ** Outbound Memory Window Translate Value Register 0 -OMWTVR0
3456 ** The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI
3469 …ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x60 /*dword 0x63,0x62,0x61,0x60*/
3472 ** Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0
3474 ** The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines
3485 …UTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x64 /*dword 0x67,0x66,0x65,0x64*/
3503 …ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x68 /*dword 0x6B,0x6A,0x69,0x68*/
3519 …UTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x6C /*dword 0x6F,0x6E,0x6D,0x6C*/
3533 …OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG 0x78 /*dword 0x7B,0x7A,0x79,0x78*/
3545 ** 19 0 2 ATU DRC Alias - when set, the ATU does not distinguish …
3549 ** 18 0 2 Direct Addressing Upper 2Gbytes Translation Enable - Wh…
3554 ** 17 0 2 Reserved
3555 ** 16 0 2 SERR# Manual Assertion - when set, the ATU asserts SERR…
3557 ** 15 0 2 ATU Discard Timer Status - when set, one of the 4 disca…
3560 ** 09 0 2 SERR# Detected Interrupt Enable - When set, the Intel X…
3563 ** 08 0 2 Direct Addressing Enable - Setting this bit enables dir…
3568 ** 03 0 2 ATU BIST Interrupt Enable - When set, enables an interr…
3571 ** 02 0 2 Reserved
3572 ** 01 0 2 Outbound ATU Enable - When set, enables the outbound ad…
3574 ** 00 0 2 Reserved
3577 #define ARCMSR_ATU_CONFIGURATION_REG 0x80 /*dword 0x83,0x82,0x81,0x80*/
3587 ** 18 0 2 Detected Address or Attribute Parity Error - set when a…
3615 ** 15 0 2
3617 ** 0=Outbound Transaction Queue Empty
3619 ** 14 0 2
3621 ** 0=Inbound Transaction Queue Empty
3623 ** 13 0 2 Reserved.
3624 ** 12 0 2 Discard Timer Value - This bit controls the time-out value
3626 ** A value of 0 indicates the time-out valu…
3628 ** 11 0 2 Reserved.
3639 ** 09 0 2 Reserved
3651 ** 05 0 2 Reset Internal Bus - This bit controls the reset of the Intel XScale cor…
3692 ** 04 0 2 Bus Master Indicator Enable: Provides software control for the
3700 ** 0=Private Device control Disabled - SISR register bits default to zero
3720 ** 0=Private Memory control Disabled - SDER register bit 2 default to zero
3724 #define ARCMSR_PCI_CONFIGURATION_STATUS_REG 0x84 /*dword 0x87,0x86,0x85,0x84*/
3732 ** Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the ATU Status Regis…
3737 ** Note: Bits 4:0, and bits 15 and 13:7 can result in an interrupt being driven to the Intel XScal…
3741 ** 17 0 2 VPD Address Register Updated - This bit is set when a P…
3744 ** 16 0 2 Reserved
3745 ** 15 0 2 ATU Configuration Write - This bit is set when a PCI bu…
3747 ** 14 0 2 ATU Inbound Memory Window 1 Base Updated - This bit is …
3751 ** 13 0 2 Initiated Split Completion Error Message - This bit is …
3753 ** 12 0 2 Received Split Completion Error Message - This bit is s…
3755 ** 11 0 2 Power State Transition - When the Power State Field of …
3758 ** 10 0 2 P_SERR# Asserted - set when P_SERR# is asserted on the …
3759 ** 09 0 2 Detected Parity Error - set when a parity error is dete…
3764 ** 08 0 2 ATU BIST Interrupt - When set, generates the ATU BIST S…
3767 ** register bits 3:0.
3770 ** 07 0 2 Internal Bus Master Abort - set when a transaction init…
3772 ** 04 0 2 P_SERR# Detected - set when P_SERR# is detected on the …
3773 ** 03 0 2 PCI Master Abort - set when a transaction initiated by …
3774 ** 02 0 2 PCI Target Abort (master) - set when a transaction init…
3775 ** 01 0 2 PCI Target Abort (target) - set when the ATU interface,…
3776 ** 00 0 2 PCI Master Parity Error - Master Parity Error - The ATU…
3785 #define ARCMSR_ATU_INTERRUPT_STATUS_REG 0x88 /*dword 0x8B,0x8A,0x89,0x88*/
3794 ** 31:15 0 0000H Reserved
3795 ** 14 0 2 VPD Address Register Updated Mask - Controls the settin…
3797 ** 0=Not Masked
3799 ** 13 0 2 Reserved
3800 ** 12 0 2 Configuration Register Write Mask - Controls the settin…
3803 ** 0=Not Masked
3808 ** 0=Not Masked
3810 ** 10 0 2 Initiated Split Completion Error Message Interrupt Mask…
3812 ** 0=Not Masked
3814 ** 09 0 2 Received Split Completion Error Message Interrupt Mask-…
3817 ** 0=Not Masked
3822 ** 0=Not Masked
3824 ** 07 0 2 ATU Detected Parity Error Interrupt Mask - Controls the…
3826 ** 0=Not Masked
3828 ** 06 0 2 ATU SERR# Asserted Interrupt Mask - Controls the settin…
3830 ** 0=Not Masked
3833 ** 05 0 2 ATU PCI Master Abort Interrupt Mask - Controls the sett…
3835 ** 0=Not Masked
3837 ** 04 0 2 ATU PCI Target Abort (Master) Interrupt Mask- Controls …
3839 ** 0=Not Masked
3841 ** 03 0 2 ATU PCI Target Abort (Target) Interrupt Mask- Controls …
3843 ** 0=Not Masked
3845 ** 02 0 2 ATU PCI Master Parity Error Interrupt Mask - Controls t…
3847 ** 0=Not Masked
3849 ** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU …
3852 ** 0=SERR# Not Asserted due to error
3854 ** 00 0 2 ATU ECC Target Abort Enable - Controls the ATU response…
3858 ** 0=Disconnect with data
3866 #define ARCMSR_ATU_INTERRUPT_MASK_REG 0x8C /*dword 0x8F,0x8E,0x8D,0x8C*/
3875 ** . Bits 31 through 12 of the IABAR3 is either read/write bits or read only with a value of 0 dep…
3899 ** 03 0 2 Prefetchable Indicator - When set, defines the memory s…
3903 ** 00 0 2 Memory Space Indicator - This bit field describes memor…
3908 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG 0x90 /*dword 0x93,0x92,0x91,0x90*/
3924 ** 31:0 00000H Translation Upper Base Address 3 - Together with the Tr…
3928 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG 0x94 /*dword 0x97,0x96,0x95,0x…
3945 ** one to one correspondence. A value of 0 in a bit within the IALR3 makes the corresponding bit
3946 ** within the IABAR3 a read only bit which always returns 0. A value of 1 in a bit within the IALR3
3958 #define ARCMSR_INBOUND_ATU_LIMIT3_REG 0x98 /*dword 0x9B,0x9A,0x99,0x98*/
3974 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG 0x9C /*dword 0x9F,0x9E,0x9D,0x9C*/
3984 ** Note: Bits 15:11 of the configuration cycle address for Type 0 configuration cycles are defined…
3986 ** Type 0 configuration cycle, the OCCAR should always be loaded based on the PCI-X definition for
3987 ** the Type 0 configuration cycle address. When operating in Conventional mode, the 80331 clears
3988 ** bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI…
3996 … ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG 0xA4 /*dword 0xA7,0xA6,0xA5,0xA4*/
4016 …e ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG 0xAC /*dword 0xAF,0xAE,0xAD,0xAC*/
4031 #define ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG 0xB8 /*byte*/
4046 #define ARCMSR_VPD_NEXT_ITEM_PTR_REG 0xB9 /*byte*/
4058 ** 15 0 2 Flag - A flag is used to indicate when a transfer of data between the …
4061 ** 14:0 0000H VPD Address - This register is written to set the DWORD-aligned byte a…
4065 #define ARCMSR_VPD_ADDRESS_REG 0xBA /*word 0xBB,0xBA*/
4076 #define ARCMSR_VPD_DATA_REG 0xBC /*dword 0xBF,0xBE,0xBD,0xBC*/
4092 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG 0xC0 /*byte*/
4106 #define ARCMSR_POWER_NEXT_ITEM_PTR_REG 0xC1 /*byte*/
4118 ** 10 0 2 D2_Support - This bit is set to 0 2 indicating that the…
4122 ** 5 0 2 DSI - This field is set to 0 2 meaning that this functi…
4124 ** 4 0 2 Reserved.
4125 ** 3 0 2 PME Clock - Since the 80331 does not support PME# signa…
4126 ** 2:0 010 2 Version - Setting these bits to 010 2 means that this f…
4130 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG 0xC2 /*word 0xC3,0xC2*/
4140 ** 15 0 2 PME_Status - This function is not capable of asserting …
4143 ** 8 0 2 PME_En - This bit is hardwired to read-only 0 2 since t…
4146 ** 1:0 00 2 Power State - This 2-bit field is used both to determin…
4156 #define ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG 0xC4 /*word 0xC5,0xC4*/
4171 #define ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG 0xE0 /*byte*/
4185 ** initialized at P_RST# assertion to Retry Type 0 configuration cycles (bit 2 of PCSR). Typically,
4198 #define ARCMSR_PCIX_NEXT_ITEM_PTR_REG 0xE1 /*byte*/
4211 ** 0 1
4222 ** 0 512
4226 ** 1 0 2
4229 ** 0 0 2 Data Parity Error Recovery Enable - The device driver s…
4230 ** recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the dev…
4234 #define ARCMSR_PCIX_COMMAND_REG 0xE2 /*word 0xE3,0xE2*/
4244 ** 29 0 2 Received Split Completion Error Message - This bit is s…
4247 ** 0=no Split Completion error message received.
4260 ** 19 0 2 Unexpected Split Completion - This bit is set when an u…
4262 ** 0=no unexpected Split Completion has been received.
4264 ** 18 0 2 Split Completion Discarded - This bit is set when the d…
4268 ** 0=no Split Completion has been discarded.
4275 ** 80331 with no bridge and central resource disabled (BRG_EN=0, ARB_EN=0),
4279 ** 0=The bus is 32 bits wide.
4284 …nfiguration Write transaction, the function must update this register with the contents of AD[7::0]
4290 ** 3. AD[1::0] are 00b (Type 0 configuration transaction).
4294 ** Type 0 configuration transaction that is assigned to the device containing this function by …
4303 ** 3. AD[1::0] are 00b (Type 0 configuration transaction).
4305 ** 2:0 000 2 Function Number - This register is read for diagnostic …
4306 … function; i.e., the number in the Function Number field (AD[10::08]) of the address of a Type 0
4312 #define ARCMSR_PCIX_STATUS_REG 0xE4 /*dword 0xE7,0xE6,0xE5,0xE4*/
4377 ** based on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). When set, a
4384 ** on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). The ITQ for this
4479 ** Completion Message, (with Message class=0h - Write Completion Class and Message index =
4494 ** IB_C/BE[7:0]# to mask the bytes not written in the 64-bit data phase. Write data is transferred
4692 ** 1.Inbound ATU Base Address Register 0 (IABAR0)
4693 ** 2.Inbound ATU Limit Register 0 (IALR0)
4718 ** 0010H Inbound Message Register 0 ]
4720 ** 0018H Outbound Message Register 0 ]
4743 ** 0FFCH ] 1004 Index Registers
4773 ** local_buffer 0x0050 ....0x0FFF
4840 #define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 /*dword 0x13,0x12,0x11,0x10*/
4841 #define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 /*dword 0x17,0x16,0x15,0x14*/
4856 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 /*dword 0x1B,0x1A,0x19,0x18*/
4857 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/
4873 ** Writing a value of 0 to any bit does not change the value of that bit and does not cause an i…
4882 ** Writing a value of 0 to any bit does not change the value of that bit and does not clear the …
4894 ** 31 0 2 Error Interrupt - Generate an Error Interrupt to the In…
4899 #define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/
4915 ** 31:07 0000000H 0 2 Reserved
4916 ** 06 0 2 Index Register Interrupt - This bit is set by the MU hardware
4918 ** 05 0 2 Outbound Free Queue Full Interrupt - This bit is set
4921 ** 04 0 2 Inbound Post Queue Interrupt - This bit is set by the MU hardware …
4927 ** 03 0 2 Error Doorbell Interrupt - This bit is set when the Error Interrup…
4929 ** 02 0 2 Inbound Doorbell Interrupt - This bit is set when at least one
4932 ** 01 0 2 Inbound Message 1 Interrupt - This bit is set by the MU hardware w…
4933 ** 00 0 2 Inbound Message 0 Interrupt - This bit is set by the MU hardware w…
4936 #define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/
4937 #define ARCMSR_MU_INBOUND_INDEX_INT 0x40
4938 #define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20
4939 #define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10
4940 #define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08
4941 #define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04
4942 #define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02
4943 #define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01
4954 ** 31:07 000000H 0 2 Reserved
4955 ** 06 0 2 Index Register Interrupt Mask - When set, this bit masks the interr…
4957 ** 05 0 2 Outbound Free Queue Full Interrupt Mask - When set, this bit masks …
4959 ** 04 0 2 Inbound Post Queue Interrupt Mask - When set, this bit masks the in…
4961 ** 03 0 2 Error Doorbell Interrupt Mask - When set, this bit masks the Error …
4963 ** 02 0 2 Inbound Doorbell Interrupt Mask - When set, this bit masks the inte…
4965 ** 01 0 2 Inbound Message 1 Interrupt Mask - When set, this bit masks the Inb…
4967 ** 00 0 2 Inbound Message 0 Interrupt Mask - When set,
4968 … this bit masks the Inbound Message 0 Interrupt generated by a write to the Inbound Me…
4971 #define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 /*dword 0x2B,0x2A,0x29,0x28*/
4972 #define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40
4973 #define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20
4974 #define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10
4975 #define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08
4976 #define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04
4977 #define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02
4978 #define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01
4991 ** 31 0 2 Reserved
4992 ** 30 0 2 Reserved.
4993 ** 29 0 2 Reserved
5007 #define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C /*dword 0x2F,0x2E,0x2D,0x2C*/
5021 ** 04 0 2 PCI Interrupt - This bit is set when the PCI Interrupt …
5023 ** 03 0 2 Outbound Post Queue Interrupt - This bit is set when da…
5025 ** 02 0 2 Outbound Doorbell Interrupt - This bit is set when at l…
5028 ** 01 0 2 Outbound Message 1 Interrupt - This bit is set by the M…
5030 ** 00 0 2 Outbound Message 0 Interrupt - This bit is set by the M…
5034 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 /*dword 0x33,0x32,0x31,0x30*/
5035 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10
5036 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08
5037 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04
5038 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02
5039 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01
5052 ** 04 0 2 PCI Interrupt Mask - When set, this bit masks the inter…
5054 ** 03 0 2 Outbound Post Queue Interrupt Mask - When set, this bit…
5056 ** 02 0 2 Outbound Doorbell Interrupt Mask - When set, this bit m…
5058 ** 01 0 2 Outbound Message 1 Interrupt Mask - When set, this bit …
5060 ** 00 0 2 Outbound Message 0 Interrupt Mask- When set, this bit m…
5061 … generated by a write to the Outbound Message 0 Register.
5064 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 /*dword 0x37,0x36,0x35,0x34*/
5065 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10
5066 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08
5067 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04
5068 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02
5069 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01
5070 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F
5076 #define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/
5077 #define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/
5125 …I transaction to the inbound or outbound queue ports with null byte enables (P_C/BE[3:0]#=1111 2 )
5344 ** FFFF E310H Inbound Message Register 0 | Available through
5346 ** FFFF E318H Outbound Message Register 0 |
5399 ** 00 0 2 Circular Queue Enable - This bit enables or disables the Ci…
5405 #define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350
5406 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020
5407 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010
5408 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008
5409 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004
5410 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002
5411 #define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 /*0:disable 1:enable*/
5429 #define ARCMSR_MU_QUEUE_BASE_ADDRESS_REG 0xFFFFE354
5447 #define ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG 0xFFFFE360
5463 #define ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG 0xFFFFE364
5479 #define ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG 0xFFFFE368
5495 #define ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG 0xFFFFE36C
5512 … ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 /*1004 dwords 0x0050....0x0FFC, 4016 byte…
5520 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61)
5535 ** The following are command code defined in raid controller Command code 0x10--0x1? are used f…
5537 ** Command code 0x20--0x?? always check the password, password must be entered to enable these …
5540 ** GUI_SET_SERIAL=0x10,
5553 ** // GUI_QUICK_CREATE=0x20, (function removed)
5554 ** GUI_GET_INFO_R=0x20,
5560 ** GUI_MUTE_BEEPER=0x30,
5571 ** GUI_CREATE_PASS_THROUGH=0x40,
5576 ** GUI_CREATE_RAIDSET=0x50,
5583 ** GUI_CREATE_VOLUME=0x60,
5593 ** byte 0,1 : length
5594 ** byte 2 : command code 0x10
5595 ** byte 3 : password length (should be 0x0f)
5596 ** byte 4-0x13 : should be "ArEcATecHnoLogY"
5597 ** byte 0x14--0x23 : Serial number string (must be 16 bytes)
5599 ** byte 0,1 : length
5600 ** byte 2 : command code 0x11
5601 ** byte 3 : password length (should be 0x08)
5602 ** byte 4-0x13 : should be "ArEcAvAr"
5603 ** byte 0x14--0x3B : vendor string (must be 40 bytes)
5605 ** byte 0,1 : length
5606 ** byte 2 : command code 0x12
5607 ** byte 3 : password length (should be 0x08)
5608 ** byte 4-0x13 : should be "ArEcAvAr"
5609 ** byte 0x14--0x1B : model string (must be 8 bytes)
5611 ** byte 0,1 : length
5612 ** byte 2 : command code 0x13
5615 ** byte 0,1 : length
5616 ** byte 2 : command code 0x14
5618 ** byte 4-0x?? : user password to be checked
5620 ** byte 0,1 : length
5621 ** byte 2 : command code 0x15
5622 ** GUI_HTTP : HTTP interface (reserved for Http proxy service)(0x16)
5625 ** byte 0,1 : length
5626 ** byte 2 : command code 0x17
5627 ** byte 3 : password length (should be 0x08)
5628 ** byte 4-0x13 : should be "ArEcAvAr"
5629 ** byte 0x14--0x19 : Ethernet MAC address (must be 6 bytes)
5631 ** byte 0,1 : length
5632 ** byte 2 : command code 0x18
5633 ** byte 3 : Page# (0/1/2/3) (0xff --> clear OEM logo)
5634 ** byte 4/5/6/7 : 0x55/0xaa/0xa5/0x5a
5638 ** byte 0,1 : length
5639 ** byte 2 : command code 0x19
5641 ** byte 0,1 : length
5642 ** byte 2 : command code 0x1a
5643 ** byte 3 : Event Page (0:1st page/1/2/3:last page)
5645 ** byte 0,1 : length
5646 ** byte 2 : command code 0x1b
5651 ** byte 7/8 : Fan#0 (RPM)
5653 ** byte 11/12 : Voltage#0 original value in *1000
5654 ** byte 13/14 : Voltage#0 value
5659 ** byte 23 : Temp#0
5661 ** byte 25 : Power indicator (bit0 : power#0, bit1 : power#1)
5664 ** byte 0,1 : length
5665 ** byte 2 : command code 0x20
5674 ** byte 0,1 : length
5675 ** byte 2 : command code 0x20
5700 ** byte 0,1 : length
5701 ** byte 2 : command code 0x21
5727 ** byte 0,1 : length
5728 ** byte 2 : command code 0x22
5729 ** byte 3 : drive # (from 0 to max-channels - 1)
5743 ** BYTE gpdRaidNumber; // 0xff if not belongs to a raid set
5749 ** byte 0,1 : length
5750 ** byte 2 : command code 0x23
5799 ** byte 0,1 : length
5800 ** byte 2 : command code 0x24
5803 ** byte 0,1 : length
5804 ** byte 2 : command code 0x30
5807 ** byte 0,1 : length
5808 ** byte 2 : command code 0x31
5809 ** byte 3 : 0->disable, 1->enable
5812 ** byte 0,1 : length
5813 ** byte 2 : command code 0x32
5818 ** byte 0,1 : length
5819 ** byte 2 : command code 0x33
5820 ** byte 3 : 0->Independent, 1->cluster
5823 ** byte 0,1 : length
5824 ** byte 2 : command code 0x34
5825 ** byte 3 : 0/1/2/3 (low->high)
5828 ** byte 0,1 : length
5829 ** byte 2 : command code 0x35
5830 ** byte 3 : 0/1/2/3 (133/100/66/33)
5833 ** byte 0,1 : length
5834 ** byte 2 : command code 0x36
5838 ** byte 0,1 : length
5839 ** byte 2 : command code 0x37
5840 ** byte 3 : 0->COMA (term port), 1->COMB (debug port)
5841 ** byte 4 : 0/1/2/3/4/5/6/7 (1200/2400/4800/9600/19200/38400/57600/115200)
5842 ** byte 5 : data bit (0:7 bit, 1:8 bit : must be 8 bit)
5843 ** byte 6 : stop bit (0:1, 1:2 stop bits)
5844 ** byte 7 : parity (0:none, 1:off, 2:even)
5845 ** byte 8 : flow control (0:none, 1:xon/xoff, 2:hardware => must use none)
5848 ** byte 0,1 : length
5849 ** byte 2 : command code 0x38
5852 ** byte 0,1 : length
5853 ** byte 2 : command code 0x39
5854 ** byte 3 : 0:dhcp disabled, 1:dhcp enabled
5858 ** byte 0,1 : length
5859 ** byte 2 : command code 0x40
5861 ** byte 4 : scsi channel (0/1)
5862 ** byte 5 : scsi id (0-->15)
5863 ** byte 6 : scsi lun (0-->7)
5866 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi)
5867 ** (0/1/2/3/4, 33/66/100/133/150 for ide )
5870 ** byte 0,1 : length
5871 ** byte 2 : command code 0x41
5873 ** byte 4 : scsi channel (0/1)
5874 ** byte 5 : scsi id (0-->15)
5875 ** byte 6 : scsi lun (0-->7)
5878 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi)
5879 ** (0/1/2/3/4, 33/66/100/133/150 for ide )
5882 ** byte 0,1 : length
5883 ** byte 2 : command code 0x42
5887 ** byte 0,1 : length
5888 ** byte 2 : command code 0x43
5889 ** byte 3 : Flash Method(0:flash selected, 1:flash not selected)
5894 ** byte 0,1 : length
5895 ** byte 2 : command code 0x50
5897 ** byte 7-22 : raidset name (if byte 7 == 0:use default)
5900 ** byte 0,1 : length
5901 ** byte 2 : command code 0x51
5905 ** byte 0,1 : length
5906 ** byte 2 : command code 0x52
5909 ** byte 8/9/10 : (8:0 no change, 1 change, 0xff:terminate, 9:new raid level,10:new stripe …
5913 ** byte 0,1 : length
5914 ** byte 2 : command code 0x53
5918 ** byte 0,1 : length
5919 ** byte 2 : command code 0x54
5923 ** byte 0,1 : length
5924 ** byte 2 : command code 0x55
5928 ** byte 0,1 : length
5929 ** byte 2 : command code 0x60
5931 ** byte 4-19 : volume set name (if byte4 == 0, use default)
5934 ** byte 29 : stripe size (0/1/2/3/4/5->4/8/16/32/64/128K)
5940 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi)
5941 ** (0/1/2/3/4->33/66/100/133/150 for IDE )
5945 ** byte 0,1 : length
5946 ** byte 2 : command code 0x61
5948 ** byte 4-19 : new volume set name (if byte4 == 0, not change)
5951 ** byte 29 : new stripe size (0/1/2/3/4/5->4/8/16/32/64/128K)
5957 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi)
5958 ** (0/1/2/3/4->33/66/100/133/150 for IDE )
5961 ** byte 0,1 : length
5962 ** byte 2 : command code 0x62
5966 ** byte 0,1 : length
5967 ** byte 2 : command code 0x63
5971 ** byte 0,1 : length
5972 ** byte 2 : command code 0x64
5976 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61)
5980 ** #define GUI_OK 0x41
5981 ** #define GUI_RAIDSET_NOT_NORMAL 0x42
5982 ** #define GUI_VOLUMESET_NOT_NORMAL 0x43
5983 ** #define GUI_NO_RAIDSET 0x44
5984 ** #define GUI_NO_VOLUMESET 0x45
5985 ** #define GUI_NO_PHYSICAL_DRIVE 0x46
5986 ** #define GUI_PARAMETER_ERROR 0x47
5987 ** #define GUI_UNSUPPORTED_COMMAND 0x48
5988 ** #define GUI_DISK_CONFIG_CHANGED 0x49
5989 ** #define GUI_INVALID_PASSWORD 0x4a
5990 ** #define GUI_NO_DISK_SPACE 0x4b
5991 ** #define GUI_CHECKSUM_ERROR 0x4c
5992 ** #define GUI_PASSWORD_REQUIRED 0x4d