Lines Matching refs:HBF_MessageUnit

1176 			CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_high, 0);  in arcmsr_post_srb()
1177 			CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp);  in arcmsr_post_srb()
2243 	CHIP_REG_WRITE32(HBF_MessageUnit, 0, reply_post_consumer_index, doneq_index);  in arcmsr_hbf_postqueue_isr()
2416 	host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status) &  in arcmsr_handle_hbf_isr()
2432 		host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status);  in arcmsr_handle_hbf_isr()
2512 		u_int32_t outMsg1 = CHIP_REG_READ32(HBF_MessageUnit, 0, outbound_msgaddr1);  in arcmsr_polling_devmap()
2516 		CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);  in arcmsr_polling_devmap()
2518 		CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);  in arcmsr_polling_devmap()
4022 	CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);  in arcmsr_get_hbf_config()
4357 			CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);  in arcmsr_iop_confirm()
4359 			CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);  in arcmsr_iop_confirm()
4482 …CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, (u_int32_t)(host_buffer_dma | 1));  /* host…  in arcmsr_map_free_srb()
4483 …CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr1, (u_int32_t)((host_buffer_dma >> 16) >> 16))…  in arcmsr_map_free_srb()
4484 …CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBFMU_DOORBELL_SYNC1);       /* set …  in arcmsr_map_free_srb()
4485 …acb->firm_PicStatus = CHIP_REG_READ32(HBF_MessageUnit, 0, outbound_msgaddr1);	/* get firmware spec…  in arcmsr_map_free_srb()
4885 		CHIP_REG_WRITE32(HBF_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/  in arcmsr_map_pcireg()
4886 …CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize…  in arcmsr_map_pcireg()