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24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
36  * for Atlantic registers.
47 /* register address for bitfield rx dma good octet counter lsw [1f:0] */
49 /* register address for bitfield rx dma good packet counter lsw [1f:0] */
51 /* register address for bitfield tx dma good octet counter lsw [1f:0] */
53 /* register address for bitfield tx dma good packet counter lsw [1f:0] */
56 /* register address for bitfield rx dma good octet counter msw [3f:20] */
58 /* register address for bitfield rx dma good packet counter msw [3f:20] */
60 /* register address for bitfield tx dma good octet counter msw [3f:20] */
62 /* register address for bitfield tx dma good packet counter msw [3f:20] */
64 /* register address for bitfield rx lro coalesced packet count lsw [1f:0] */
67 /* preprocessor definitions for msm rx errors counter register */
70 /* preprocessor definitions for msm rx unicast frames counter register */
73 /* preprocessor definitions for msm rx multicast frames counter register */
76 /* preprocessor definitions for msm rx broadcast frames counter register */
79 /* preprocessor definitions for msm rx broadcast octets counter register 1 */
82 /* preprocessor definitions for msm rx broadcast octets counter register 2 */
85 /* preprocessor definitions for msm rx unicast octets counter register 0 */
88 /* preprocessor definitions for rx dma statistics counter 7 */
91 /* preprocessor definitions for msm tx unicast frames counter register */
94 /* preprocessor definitions for msm tx multicast frames counter register */
99 *   Preprocessor definitions for Global FW Image Identification 1
105 /* preprocessor definitions for global mif identification */
108 /* register address for bitfield iamr_lsw[1f:0] */
110 /* register address for bitfield rx dma drop packet counter [1f:0] */
113 /* register address for bitfield imcr_lsw[1f:0] */
115 /* register address for bitfield imsr_lsw[1f:0] */
117 /* register address for bitfield itr_reg_res_dsbl */
119 /* bitmask for bitfield itr_reg_res_dsbl */
123 /* register address for bitfield iscr_lsw[1f:0] */
125 /* register address for bitfield isr_lsw[1f:0] */
127 /* register address for bitfield itr_reset */
129 /* bitmask for bitfield itr_reset */
133 /* register address for bitfield dca{d}_cpuid[7:0] */
135 /* bitmask for bitfield dca{d}_cpuid[7:0] */
139 /* register address for bitfield dca_en */
143 *   Preprocessor definitions for MIF Power Gating Enable Control
151 *   Preprocessor definitions for Global General Provisioning 9
159 *   Preprocessor definitions for Global NVR Provisioning 2
167 *   Preprocessor definitions for Global NVR Interface 1
175  * preprocessor definitions for the bitfield "dca_en".
179 /* register address for bitfield dca_en */
181 /* bitmask for bitfield dca_en */
183 /* inverted bitmask for bitfield dca_en */
194 *   Preprocessor definitions for the bitfield "MPI register reset disable".
197 /*! \brief Register address for bitfield MPI register reset disable */
199 /*! \brief Bitmask for bitfield MPI register reset disable */
201 /*! \brief Inverted bitmask for bitfield MPI register reset disable */
213  * preprocessor definitions for the bitfield "dca_mode[3:0]".
217 /* register address for bitfield dca_mode[3:0] */
219 /* bitmask for bitfield dca_mode[3:0] */
221 /* inverted bitmask for bitfield dca_mode[3:0] */
231  * preprocessor definitions for the bitfield "desc{d}_data_size[4:0]".
236 /* register address for bitfield desc{d}_data_size[4:0] */
238 /* bitmask for bitfield desc{d}_data_size[4:0] */
240 /* inverted bitmask for bitfield desc{d}_data_size[4:0] */
250  * preprocessor definitions for the bitfield "dca{d}_desc_en".
255 /* register address for bitfield dca{d}_desc_en */
257 /* bitmask for bitfield dca{d}_desc_en */
259 /* inverted bitmask for bitfield dca{d}_desc_en */
269  * preprocessor definitions for the bitfield "desc{d}_en".
274 /* register address for bitfield desc{d}_en */
276 /* bitmask for bitfield desc{d}_en */
278 /* inverted bitmask for bitfield desc{d}_en */
288  * preprocessor definitions for the bitfield "desc{d}_hdr_size[4:0]".
293 /* register address for bitfield desc{d}_hdr_size[4:0] */
295 /* bitmask for bitfield desc{d}_hdr_size[4:0] */
297 /* inverted bitmask for bitfield desc{d}_hdr_size[4:0] */
307  * preprocessor definitions for the bitfield "desc{d}_hdr_split".
312 /* register address for bitfield desc{d}_hdr_split */
314 /* bitmask for bitfield desc{d}_hdr_split */
316 /* inverted bitmask for bitfield desc{d}_hdr_split */
326  * preprocessor definitions for the bitfield "desc{d}_hd[c:0]".
331 /* register address for bitfield desc{d}_hd[c:0] */
333 /* bitmask for bitfield desc{d}_hd[c:0] */
335 /* inverted bitmask for bitfield desc{d}_hd[c:0] */
343  * preprocessor definitions for the bitfield "desc{d}_len[9:0]".
348 /* register address for bitfield desc{d}_len[9:0] */
350 /* bitmask for bitfield desc{d}_len[9:0] */
352 /* inverted bitmask for bitfield desc{d}_len[9:0] */
362  * preprocessor definitions for the bitfield "desc{d}_reset".
367 /* register address for bitfield desc{d}_reset */
369 /* bitmask for bitfield desc{d}_reset */
371 /* inverted bitmask for bitfield desc{d}_reset */
381  * preprocessor definitions for the bitfield rdm_desc_init_i.
385 /* register address for bitfield rdm_desc_init_i */
387 /* bitmask for bitfield rdm_desc_init_i */
389 /* inverted bitmask for bitfield rdm_desc_init_i */
399  * preprocessor definitions for the bitfield "int_desc_wrb_en".
403 /* register address for bitfield int_desc_wrb_en */
405 /* bitmask for bitfield int_desc_wrb_en */
407 /* inverted bitmask for bitfield int_desc_wrb_en */
417  * preprocessor definitions for the bitfield "dca{d}_hdr_en".
422 /* register address for bitfield dca{d}_hdr_en */
424 /* bitmask for bitfield dca{d}_hdr_en */
426 /* inverted bitmask for bitfield dca{d}_hdr_en */
436  * preprocessor definitions for the bitfield "dca{d}_pay_en".
441 /* register address for bitfield dca{d}_pay_en */
443 /* bitmask for bitfield dca{d}_pay_en */
445 /* inverted bitmask for bitfield dca{d}_pay_en */
455  * Preprocessor definitions for the bitfield "rdm_int_rim_en".
459 /* Register address for bitfield rdm_int_rim_en */
461 /* Bitmask for bitfield rdm_int_rim_en */
463 /* Inverted bitmask for bitfield rdm_int_rim_en */
473  * preprocessor definitions for general interrupt mapping register
480  * preprocessor definitions for general interrupt status register
487  * preprocessor definitions for interrupt global control register
493  * preprocessor definitions for interrupt throttle register
499 /* Register address for bitfield imr_link_en */
501 /* Bitmask for bitfield imr_link_en */
503 /* Inverted bitmask for bitfield imr_link_en */
512 /* Register address for bitfield imr_link[4:0] */
514 /* Bitmask for bitfield imr_link[4:0] */
516 /* Inverted bitmask for bitfield imr_link[4:0] */
527 *  Preprocessor definitions for the bitfield "imr_mif{M}_en".
531 /* Register address for bitfield imr_mif{M}_en */
538 /* Bitmask for bitfield imr_mif{M}_en */
545 /* Inverted bitmask for bitfield imr_mif{M}_en */
565 *   Preprocessor definitions for the bitfield "imr_mif{M}[4:0]".
569 /* Register address for bitfield imr_mif{M}[4:0] */
576 /* Bitmask for bitfield imr_mif{M}[4:0] */
583 /* Inverted bitmask for bitfield imr_mif{M}[4:0] */
603 /* Register address for bitfield int_mode[1:0] */
605 /* Bitmask for bitfield int_mode[1:0] */
607 /* Inverted bitmask for bitfield int_mode[1:0] */
616 /* Register address for bitfield isr_cor_en */
618 /* Bitmask for bitfield isr_cor_en */
620 /* Inverted bitmask for bitfield isr_cor_en */
630 /* Register address for bitfield iamr_clr_en */
632 /* Bitmask for bitfield iamr_clr_en */
634 /* Inverted bitmask for bitfield iamr_clr_en */
644  * preprocessor definitions for rx dma descriptor base address lsw
652  * preprocessor definitions for rx dma descriptor base address msw
660  * preprocessor definitions for rx dma descriptor status register
667  * preprocessor definitions for rx dma descriptor tail pointer register
674  * Preprocessor definitions for RX Interrupt Moderation Control Register
681  * preprocessor definitions for rx filter multicast filter mask register
687  * preprocessor definitions for rx filter multicast filter register
694  * Preprocessor definitions for RX Filter RSS Control Register 1
700  * Preprocessor definitions for RX Filter Control Register 2
706  * preprocessor definitions for the bitfield "tx dma debug control [1f:0]".
710 /* register address for bitfield tx dma debug control [1f:0] */
712 /* bitmask for bitfield tx dma debug control [1f:0] */
714 /* inverted bitmask for bitfield tx dma debug control [1f:0] */
724  * preprocessor definitions for tx dma descriptor base address lsw
732  * preprocessor definitions for tx dma descriptor tail pointer register
739  * preprocessor definitions for the bitfield "dma_sys_loopback".
743 /* register address for bitfield dma_sys_loopback */
745 /* bitmask for bitfield dma_sys_loopback */
747 /* inverted bitmask for bitfield dma_sys_loopback */
757  * preprocessor definitions for the bitfield "rx_tc_mode".
761 /* register address for bitfield rx_tc_mode */
763 /* bitmask for bitfield rx_tc_mode */
765 /* inverted bitmask for bitfield rx_tc_mode */
775  * preprocessor definitions for the bitfield "rx_buf_en".
779 /* register address for bitfield rx_buf_en */
781 /* bitmask for bitfield rx_buf_en */
783 /* inverted bitmask for bitfield rx_buf_en */
793  * preprocessor definitions for the bitfield "rx{b}_hi_thresh[d:0]".
798 /* register address for bitfield rx{b}_hi_thresh[d:0] */
800 /* bitmask for bitfield rx{b}_hi_thresh[d:0] */
802 /* inverted bitmask for bitfield rx{b}_hi_thresh[d:0] */
812  * preprocessor definitions for the bitfield "rx{b}_lo_thresh[d:0]".
817 /* register address for bitfield rx{b}_lo_thresh[d:0] */
819 /* bitmask for bitfield rx{b}_lo_thresh[d:0] */
821 /* inverted bitmask for bitfield rx{b}_lo_thresh[d:0] */
831  * preprocessor definitions for the bitfield "rx_fc_mode[1:0]".
835 /* register address for bitfield rx_fc_mode[1:0] */
837 /* bitmask for bitfield rx_fc_mode[1:0] */
839 /* inverted bitmask for bitfield rx_fc_mode[1:0] */
849  * preprocessor definitions for the bitfield "rx{b}_buf_size[8:0]".
854 /* register address for bitfield rx{b}_buf_size[8:0] */
856 /* bitmask for bitfield rx{b}_buf_size[8:0] */
858 /* inverted bitmask for bitfield rx{b}_buf_size[8:0] */
868  * preprocessor definitions for the bitfield "rx{b}_xoff_en".
873 /* register address for bitfield rx{b}_xoff_en */
875 /* bitmask for bitfield rx{b}_xoff_en */
877 /* inverted bitmask for bitfield rx{b}_xoff_en */
887  * preprocessor definitions for the bitfield "l2_bc_thresh[f:0]".
891 /* register address for bitfield l2_bc_thresh[f:0] */
893 /* bitmask for bitfield l2_bc_thresh[f:0] */
895 /* inverted bitmask for bitfield l2_bc_thresh[f:0] */
905  * preprocessor definitions for the bitfield "l2_bc_en".
909 /* register address for bitfield l2_bc_en */
911 /* bitmask for bitfield l2_bc_en */
913 /* inverted bitmask for bitfield l2_bc_en */
923  * preprocessor definitions for the bitfield "l2_bc_act[2:0]".
927 /* register address for bitfield l2_bc_act[2:0] */
929 /* bitmask for bitfield l2_bc_act[2:0] */
931 /* inverted bitmask for bitfield l2_bc_act[2:0] */
941  * preprocessor definitions for the bitfield "l2_mc_en{f}".
946 /* register address for bitfield l2_mc_en{f} */
948 /* bitmask for bitfield l2_mc_en{f} */
950 /* inverted bitmask for bitfield l2_mc_en{f} */
960  * preprocessor definitions for the bitfield "l2_promis_mode".
964 /* register address for bitfield l2_promis_mode */
966 /* bitmask for bitfield l2_promis_mode */
968 /* inverted bitmask for bitfield l2_promis_mode */
978  * preprocessor definitions for the bitfield "l2_uc_act{f}[2:0]".
983 /* register address for bitfield l2_uc_act{f}[2:0] */
985 /* bitmask for bitfield l2_uc_act{f}[2:0] */
987 /* inverted bitmask for bitfield l2_uc_act{f}[2:0] */
997  * preprocessor definitions for the bitfield "l2_uc_en{f}".
1002 /* register address for bitfield l2_uc_en{f} */
1004 /* bitmask for bitfield l2_uc_en{f} */
1006 /* inverted bitmask for bitfield l2_uc_en{f} */
1015 /* register address for bitfield l2_uc_da{f}_lsw[1f:0] */
1017 /* register address for bitfield l2_uc_da{f}_msw[f:0] */
1019 /* bitmask for bitfield l2_uc_da{f}_msw[f:0] */
1025  * Preprocessor definitions for the bitfield "l2_mc_accept_all".
1029 /* Register address for bitfield l2_mc_accept_all */
1031 /* Bitmask for bitfield l2_mc_accept_all */
1033 /* Inverted bitmask for bitfield l2_mc_accept_all */
1048  * preprocessor definitions for the bitfield "rss_key_addr[4:0]".
1052 /* register address for bitfield rss_key_addr[4:0] */
1054 /* bitmask for bitfield rss_key_addr[4:0] */
1056 /* inverted bitmask for bitfield rss_key_addr[4:0] */
1066  * preprocessor definitions for the bitfield "rss_key_wr_data[1f:0]".
1070 /* register address for bitfield rss_key_wr_data[1f:0] */
1072 /* bitmask for bitfield rss_key_wr_data[1f:0] */
1074 /* inverted bitmask for bitfield rss_key_wr_data[1f:0] */
1084  * preprocessor definitions for the bitfield "rss_key_rd_data[1f:0]".
1088 /* register address for bitfield rss_key_rd_data[1f:0] */
1090 /* bitmask for bitfield rss_key_rd_data[1f:0] */
1092 /* inverted bitmask for bitfield rss_key_rd_data[1f:0] */
1102  * preprocessor definitions for the bitfield "rss_key_wr_en_i".
1106 /* register address for bitfield rss_key_wr_en_i */
1108 /* bitmask for bitfield rss_key_wr_en_i */
1110 /* inverted bitmask for bitfield rss_key_wr_en_i */
1120  * preprocessor definitions for the bitfield "rss_redir_addr[3:0]".
1124 /* register address for bitfield rss_redir_addr[3:0] */
1126 /* bitmask for bitfield rss_redir_addr[3:0] */
1128 /* inverted bitmask for bitfield rss_redir_addr[3:0] */
1138  * preprocessor definitions for the bitfield "rss_redir_wr_data[f:0]".
1142 /* register address for bitfield rss_redir_wr_data[f:0] */
1144 /* bitmask for bitfield rss_redir_wr_data[f:0] */
1146 /* inverted bitmask for bitfield rss_redir_wr_data[f:0] */
1156  * preprocessor definitions for the bitfield "rss_redir_wr_en_i".
1160 /* register address for bitfield rss_redir_wr_en_i */
1162 /* bitmask for bitfield rss_redir_wr_en_i */
1164 /* inverted bitmask for bitfield rss_redir_wr_en_i */
1174  * preprocessor definitions for the bitfield "tpo_rpf_sys_loopback".
1178 /* register address for bitfield tpo_rpf_sys_loopback */
1180 /* bitmask for bitfield tpo_rpf_sys_loopback */
1182 /* inverted bitmask for bitfield tpo_rpf_sys_loopback */
1192  * preprocessor definitions for the bitfield "vl_inner_tpid[f:0]".
1196 /* register address for bitfield vl_inner_tpid[f:0] */
1198 /* bitmask for bitfield vl_inner_tpid[f:0] */
1200 /* inverted bitmask for bitfield vl_inner_tpid[f:0] */
1210  * preprocessor definitions for the bitfield "vl_outer_tpid[f:0]".
1214 /* register address for bitfield vl_outer_tpid[f:0] */
1216 /* bitmask for bitfield vl_outer_tpid[f:0] */
1218 /* inverted bitmask for bitfield vl_outer_tpid[f:0] */
1228  * preprocessor definitions for the bitfield "vl_promis_mode".
1232 /* register address for bitfield vl_promis_mode */
1234 /* bitmask for bitfield vl_promis_mode */
1236 /* inverted bitmask for bitfield vl_promis_mode */
1246  * Preprocessor definitions for the bitfield "vl_accept_untagged_mode".
1250 /* Register address for bitfield vl_accept_untagged_mode */
1252 /* Bitmask for bitfield vl_accept_untagged_mode */
1254 /* Inverted bitmask for bitfield vl_accept_untagged_mode */
1264  * Preprocessor definitions for the bitfield "vl_untagged_act[2:0]".
1268 /* Register address for bitfield vl_untagged_act[2:0] */
1270 /* Bitmask for bitfield vl_untagged_act[2:0] */
1272 /* Inverted bitmask for bitfield vl_untagged_act[2:0] */
1282  * Preprocessor definitions for the bitfield "vl_en{F}".
1287 /* Register address for bitfield vl_en{F} */
1289 /* Bitmask for bitfield vl_en{F} */
1291 /* Inverted bitmask for bitfield vl_en{F} */
1301  * Preprocessor definitions for the bitfield "vl_act{F}[2:0]".
1306 /* Register address for bitfield vl_act{F}[2:0] */
1308 /* Bitmask for bitfield vl_act{F}[2:0] */
1310 /* Inverted bitmask for bitfield vl_act{F}[2:0] */
1320  * Preprocessor definitions for the bitfield "vl_id{F}[B:0]".
1325 /* Register address for bitfield vl_id{F}[B:0] */
1327 /* Bitmask for bitfield vl_id{F}[B:0] */
1329 /* Inverted bitmask for bitfield vl_id{F}[B:0] */
1339  * Preprocessor definitions for the bitfield "et_en{F}".
1344 /* Register address for bitfield et_en{F} */
1346 /* Bitmask for bitfield et_en{F} */
1348 /* Inverted bitmask for bitfield et_en{F} */
1358  * preprocessor definitions for the bitfield "et_en{f}".
1363 /* register address for bitfield et_en{f} */
1365 /* bitmask for bitfield et_en{f} */
1367 /* inverted bitmask for bitfield et_en{f} */
1377  * preprocessor definitions for the bitfield "et_up{f}_en".
1382 /* register address for bitfield et_up{f}_en */
1384 /* bitmask for bitfield et_up{f}_en */
1386 /* inverted bitmask for bitfield et_up{f}_en */
1396  * preprocessor definitions for the bitfield "et_rxq{f}_en".
1401 /* register address for bitfield et_rxq{f}_en */
1403 /* bitmask for bitfield et_rxq{f}_en */
1405 /* inverted bitmask for bitfield et_rxq{f}_en */
1415  * preprocessor definitions for the bitfield "et_up{f}[2:0]".
1420 /* register address for bitfield et_up{f}[2:0] */
1422 /* bitmask for bitfield et_up{f}[2:0] */
1424 /* inverted bitmask for bitfield et_up{f}[2:0] */
1434  * preprocessor definitions for the bitfield "et_rxq{f}[4:0]".
1439 /* register address for bitfield et_rxq{f}[4:0] */
1441 /* bitmask for bitfield et_rxq{f}[4:0] */
1443 /* inverted bitmask for bitfield et_rxq{f}[4:0] */
1453  * preprocessor definitions for the bitfield "et_mng_rxq{f}".
1458 /* register address for bitfield et_mng_rxq{f} */
1460 /* bitmask for bitfield et_mng_rxq{f} */
1462 /* inverted bitmask for bitfield et_mng_rxq{f} */
1472  * preprocessor definitions for the bitfield "et_act{f}[2:0]".
1477 /* register address for bitfield et_act{f}[2:0] */
1479 /* bitmask for bitfield et_act{f}[2:0] */
1481 /* inverted bitmask for bitfield et_act{f}[2:0] */
1491  * preprocessor definitions for the bitfield "et_val{f}[f:0]".
1496 /* register address for bitfield et_val{f}[f:0] */
1498 /* bitmask for bitfield et_val{f}[f:0] */
1500 /* inverted bitmask for bitfield et_val{f}[f:0] */
1510  * preprocessor definitions for the bitfield "vl_inner_tpid[f:0]".
1514 /* register address for bitfield vl_inner_tpid[f:0] */
1516 /* bitmask for bitfield vl_inner_tpid[f:0] */
1518 /* inverted bitmask for bitfield vl_inner_tpid[f:0] */
1528  * preprocessor definitions for the bitfield "vl_outer_tpid[f:0]".
1532 /* register address for bitfield vl_outer_tpid[f:0] */
1534 /* bitmask for bitfield vl_outer_tpid[f:0] */
1536 /* inverted bitmask for bitfield vl_outer_tpid[f:0] */
1546  * preprocessor definitions for the bitfield "vl_promis_mode".
1550 /* register address for bitfield vl_promis_mode */
1552 /* bitmask for bitfield vl_promis_mode */
1554 /* inverted bitmask for bitfield vl_promis_mode */
1564  * Preprocessor definitions for the bitfield "vl_accept_untagged_mode".
1568 /* Register address for bitfield vl_accept_untagged_mode */
1570 /* Bitmask for bitfield vl_accept_untagged_mode */
1572 /* Inverted bitmask for bitfield vl_accept_untagged_mode */
1582  * Preprocessor definitions for the bitfield "vl_untagged_act[2:0]".
1586 /* Register address for bitfield vl_untagged_act[2:0] */
1588 /* Bitmask for bitfield vl_untagged_act[2:0] */
1590 /* Inverted bitmask for bitfield vl_untagged_act[2:0] */
1600  * Preprocessor definitions for the bitfield "vl_en{F}".
1605 /* Register address for bitfield vl_en{F} */
1607 /* Bitmask for bitfield vl_en{F} */
1609 /* Inverted bitmask for bitfield vl_en{F} */
1619  * Preprocessor definitions for the bitfield "vl_act{F}[2:0]".
1624 /* Register address for bitfield vl_act{F}[2:0] */
1626 /* Bitmask for bitfield vl_act{F}[2:0] */
1628 /* Inverted bitmask for bitfield vl_act{F}[2:0] */
1638  * Preprocessor definitions for the bitfield "vl_id{F}[B:0]".
1643 /* Register address for bitfield vl_id{F}[B:0] */
1645 /* Bitmask for bitfield vl_id{F}[B:0] */
1647 /* Inverted bitmask for bitfield vl_id{F}[B:0] */
1657  * Preprocessor definitions for the bitfield "vl_rxq{F}".
1662 /* Register address for bitfield vl_rxq_en{F} */
1664 /* Bitmask for bitfield vl_rxq_en{F} */
1666 /* Inverted bitmask for bitfield vl_rxq_en{F}[ */
1676  * Preprocessor definitions for the bitfield "vl_rxq{F}[4:0]".
1681 /* Register address for bitfield vl_rxq{F}[4:0] */
1683 /* Bitmask for bitfield vl_rxq{F}[4:0] */
1685 /* Inverted bitmask for bitfield vl_rxq{F}[4:0] */
1695  * preprocessor definitions for the bitfield "et_en{f}".
1700 /* register address for bitfield et_en{f} */
1702 /* bitmask for bitfield et_en{f} */
1704 /* inverted bitmask for bitfield et_en{f} */
1714  * preprocessor definitions for the bitfield "et_up{f}_en".
1719 /* register address for bitfield et_up{f}_en */
1721 /* bitmask for bitfield et_up{f}_en */
1723 /* inverted bitmask for bitfield et_up{f}_en */
1733  * preprocessor definitions for the bitfield "et_rxq{f}_en".
1738 /* register address for bitfield et_rxq{f}_en */
1740 /* bitmask for bitfield et_rxq{f}_en */
1742 /* inverted bitmask for bitfield et_rxq{f}_en */
1752  * preprocessor definitions for the bitfield "et_up{f}[2:0]".
1757 /* register address for bitfield et_up{f}[2:0] */
1759 /* bitmask for bitfield et_up{f}[2:0] */
1761 /* inverted bitmask for bitfield et_up{f}[2:0] */
1771  * preprocessor definitions for the bitfield "et_rxq{f}[4:0]".
1776 /* register address for bitfield et_rxq{f}[4:0] */
1778 /* bitmask for bitfield et_rxq{f}[4:0] */
1780 /* inverted bitmask for bitfield et_rxq{f}[4:0] */
1790  * preprocessor definitions for the bitfield "et_mng_rxq{f}".
1795 /* register address for bitfield et_mng_rxq{f} */
1797 /* bitmask for bitfield et_mng_rxq{f} */
1799 /* inverted bitmask for bitfield et_mng_rxq{f} */
1809  * preprocessor definitions for the bitfield "et_act{f}[2:0]".
1814 /* register address for bitfield et_act{f}[2:0] */
1816 /* bitmask for bitfield et_act{f}[2:0] */
1818 /* inverted bitmask for bitfield et_act{f}[2:0] */
1828  * preprocessor definitions for the bitfield "et_val{f}[f:0]".
1833 /* register address for bitfield et_val{f}[f:0] */
1835 /* bitmask for bitfield et_val{f}[f:0] */
1837 /* inverted bitmask for bitfield et_val{f}[f:0] */
1847  * Preprocessor definitions for the bitfield "l3_l4_en{F}".
1852 /* Register address for bitfield l3_l4_en{F} */
1854 /* Bitmask for bitfield l3_l4_en{F} */
1856 /* Inverted bitmask for bitfield l3_l4_en{F} */
1866  * Preprocessor definitions for the bitfield "l3_v6_en{F}".
1870 /* Register address for bitfield l3_v6_en{F} */
1872 /* Bitmask for bitfield l3_v6_en{F} */
1874 /* Inverted bitmask for bitfield l3_v6_en{F} */
1884  * Preprocessor definitions for the bitfield "l3_sa{F}_en".
1889 /* Register address for bitfield l3_sa{F}_en */
1891 /* Bitmask for bitfield l3_sa{F}_en */
1893 /* Inverted bitmask for bitfield l3_sa{F}_en */
1903  * Preprocessor definitions for the bitfield "l3_da{F}_en".
1908 /* Register address for bitfield l3_da{F}_en */
1910 /* Bitmask for bitfield l3_da{F}_en */
1912 /* Inverted bitmask for bitfield l3_da{F}_en */
1922  * Preprocessor definitions for the bitfield "l4_sp{F}_en".
1927 /* Register address for bitfield l4_sp{F}_en */
1929 /* Bitmask for bitfield l4_sp{F}_en */
1931 /* Inverted bitmask for bitfield l4_sp{F}_en */
1941  * Preprocessor definitions for the bitfield "l4_dp{F}_en".
1946 /* Register address for bitfield l4_dp{F}_en */
1948 /* Bitmask for bitfield l4_dp{F}_en */
1950 /* Inverted bitmask for bitfield l4_dp{F}_en */
1960  * Preprocessor definitions for the bitfield "l4_prot{F}_en".
1965 /* Register address for bitfield l4_prot{F}_en */
1967 /* Bitmask for bitfield l4_prot{F}_en */
1969 /* Inverted bitmask for bitfield l4_prot{F}_en */
1979  * Preprocessor definitions for the bitfield "l3_arp{F}_en".
1984 /* Register address for bitfield l3_arp{F}_en */
1986 /* Bitmask for bitfield l3_arp{F}_en */
1988 /* Inverted bitmask for bitfield l3_arp{F}_en */
1998  * Preprocessor definitions for the bitfield "l3_l4_rxq{F}_en".
2003 /* Register address for bitfield l3_l4_RXq{F}_en */
2005 /* Bitmask for bitfield l3_l4_RXq{F}_en */
2007 /* Inverted bitmask for bitfield l3_l4_RXq{F}_en */
2017  * Preprocessor definitions for the bitfield "l3_l4_mng_RXq{F}".
2022 /* Register address for bitfield l3_l4_mng_rxq{F} */
2024 /* Bitmask for bitfield l3_l4_mng_rxq{F} */
2026 /* Inverted bitmask for bitfield l3_l4_mng_rxq{F} */
2036  * Preprocessor definitions for the bitfield "l3_l4_act{F}[2:0]".
2041 /* Register address for bitfield l3_l4_act{F}[2:0] */
2043 /* Bitmask for bitfield l3_l4_act{F}[2:0] */
2045 /* Inverted bitmask for bitfield l3_l4_act{F}[2:0] */
2055  * Preprocessor definitions for the bitfield "l3_l4_rxq{F}[4:0]".
2060 /* Register address for bitfield l3_l4_rxq{F}[4:0] */
2062 /* Bitmask for bitfield l3_l4_rxq{F}[4:0] */
2064 /* Inverted bitmask for bitfield l3_l4_rxq{F}[4:0] */
2074  * Preprocessor definitions for the bitfield "l4_prot{F}[2:0]".
2079 /* Register address for bitfield l4_prot{F}[2:0] */
2081 /* Bitmask for bitfield l4_prot{F}[2:0] */
2083 /* Inverted bitmask for bitfield l4_prot{F}[2:0] */
2093  * Preprocessor definitions for the bitfield "l4_sp{D}[F:0]".
2098 /* Register address for bitfield l4_sp{D}[F:0] */
2100 /* Bitmask for bitfield l4_sp{D}[F:0] */
2102 /* Inverted bitmask for bitfield l4_sp{D}[F:0] */
2112  * Preprocessor definitions for the bitfield "l4_dp{D}[F:0]".
2117 /* Register address for bitfield l4_dp{D}[F:0] */
2119 /* Bitmask for bitfield l4_dp{D}[F:0] */
2121 /* Inverted bitmask for bitfield l4_dp{D}[F:0] */
2131  * preprocessor definitions for the bitfield "ipv4_chk_en".
2135 /* register address for bitfield ipv4_chk_en */
2137 /* bitmask for bitfield ipv4_chk_en */
2139 /* inverted bitmask for bitfield ipv4_chk_en */
2149  * preprocessor definitions for the bitfield "desc{d}_vl_strip".
2154 /* register address for bitfield desc{d}_vl_strip */
2156 /* bitmask for bitfield desc{d}_vl_strip */
2158 /* inverted bitmask for bitfield desc{d}_vl_strip */
2168  * preprocessor definitions for the bitfield "l4_chk_en".
2172 /* register address for bitfield l4_chk_en */
2174 /* bitmask for bitfield l4_chk_en */
2176 /* inverted bitmask for bitfield l4_chk_en */
2186  * preprocessor definitions for the bitfield "reg_res_dsbl".
2190 /* register address for bitfield reg_res_dsbl */
2192 /* bitmask for bitfield reg_res_dsbl */
2194 /* inverted bitmask for bitfield reg_res_dsbl */
2204  * preprocessor definitions for the bitfield "dca{d}_cpuid[7:0]".
2209 /* register address for bitfield dca{d}_cpuid[7:0] */
2211 /* bitmask for bitfield dca{d}_cpuid[7:0] */
2213 /* inverted bitmask for bitfield dca{d}_cpuid[7:0] */
2223  * preprocessor definitions for the bitfield "lso_en[1f:0]".
2227 /* register address for bitfield lso_en[1f:0] */
2229 /* bitmask for bitfield lso_en[1f:0] */
2231 /* inverted bitmask for bitfield lso_en[1f:0] */
2241  * preprocessor definitions for the bitfield "dca_en".
2245 /* register address for bitfield dca_en */
2247 /* bitmask for bitfield dca_en */
2249 /* inverted bitmask for bitfield dca_en */
2259  * preprocessor definitions for the bitfield "dca_mode[3:0]".
2263 /* register address for bitfield dca_mode[3:0] */
2265 /* bitmask for bitfield dca_mode[3:0] */
2267 /* inverted bitmask for bitfield dca_mode[3:0] */
2277  * preprocessor definitions for the bitfield "dca{d}_desc_en".
2282 /* register address for bitfield dca{d}_desc_en */
2284 /* bitmask for bitfield dca{d}_desc_en */
2286 /* inverted bitmask for bitfield dca{d}_desc_en */
2296  * preprocessor definitions for the bitfield "desc{d}_en".
2301 /* register address for bitfield desc{d}_en */
2303 /* bitmask for bitfield desc{d}_en */
2305 /* inverted bitmask for bitfield desc{d}_en */
2315  * preprocessor definitions for the bitfield "desc{d}_hd[c:0]".
2320 /* register address for bitfield desc{d}_hd[c:0] */
2322 /* bitmask for bitfield desc{d}_hd[c:0] */
2324 /* inverted bitmask for bitfield desc{d}_hd[c:0] */
2332  * preprocessor definitions for the bitfield "desc{d}_len[9:0]".
2337 /* register address for bitfield desc{d}_len[9:0] */
2339 /* bitmask for bitfield desc{d}_len[9:0] */
2341 /* inverted bitmask for bitfield desc{d}_len[9:0] */
2351  * preprocessor definitions for the bitfield "int_desc_wrb_en".
2355 /* register address for bitfield int_desc_wrb_en */
2357 /* bitmask for bitfield int_desc_wrb_en */
2359 /* inverted bitmask for bitfield int_desc_wrb_en */
2369  * preprocessor definitions for the bitfield "desc{d}_wrb_thresh[6:0]".
2374 /* register address for bitfield desc{d}_wrb_thresh[6:0] */
2376 /* bitmask for bitfield desc{d}_wrb_thresh[6:0] */
2378 /* inverted bitmask for bitfield desc{d}_wrb_thresh[6:0] */
2388  * preprocessor definitions for the bitfield "lso_tcp_flag_first[b:0]".
2392 /* register address for bitfield lso_tcp_flag_first[b:0] */
2394 /* bitmask for bitfield lso_tcp_flag_first[b:0] */
2396 /* inverted bitmask for bitfield lso_tcp_flag_first[b:0] */
2406  * preprocessor definitions for the bitfield "lso_tcp_flag_last[b:0]".
2410 /* register address for bitfield lso_tcp_flag_last[b:0] */
2412 /* bitmask for bitfield lso_tcp_flag_last[b:0] */
2414 /* inverted bitmask for bitfield lso_tcp_flag_last[b:0] */
2424  * preprocessor definitions for the bitfield "lso_tcp_flag_mid[b:0]".
2428 /* Register address for bitfield lro_rsc_max[1F:0] */
2430 /* Bitmask for bitfield lro_rsc_max[1F:0] */
2432 /* Inverted bitmask for bitfield lro_rsc_max[1F:0] */
2442  * Preprocessor definitions for the bitfield "lro_en[1F:0]".
2446 /* Register address for bitfield lro_en[1F:0] */
2448 /* Bitmask for bitfield lro_en[1F:0] */
2450 /* Inverted bitmask for bitfield lro_en[1F:0] */
2460  * Preprocessor definitions for the bitfield "lro_ptopt_en".
2464 /* Register address for bitfield lro_ptopt_en */
2466 /* Bitmask for bitfield lro_ptopt_en */
2468 /* Inverted bitmask for bitfield lro_ptopt_en */
2478  * Preprocessor definitions for the bitfield "lro_q_ses_lmt".
2482 /* Register address for bitfield lro_q_ses_lmt */
2484 /* Bitmask for bitfield lro_q_ses_lmt */
2486 /* Inverted bitmask for bitfield lro_q_ses_lmt */
2496  * Preprocessor definitions for the bitfield "lro_tot_dsc_lmt[1:0]".
2500 /* Register address for bitfield lro_tot_dsc_lmt[1:0] */
2502 /* Bitmask for bitfield lro_tot_dsc_lmt[1:0] */
2504 /* Inverted bitmask for bitfield lro_tot_dsc_lmt[1:0] */
2514  * Preprocessor definitions for the bitfield "lro_pkt_min[4:0]".
2518 /* Register address for bitfield lro_pkt_min[4:0] */
2520 /* Bitmask for bitfield lro_pkt_min[4:0] */
2522 /* Inverted bitmask for bitfield lro_pkt_min[4:0] */
2537  * Preprocessor definitions for the bitfield "lro_tb_div[11:0]".
2541 /* Register address for bitfield lro_tb_div[11:0] */
2543 /* Bitmask for bitfield lro_tb_div[11:0] */
2545 /* Inverted bitmask for bitfield lro_tb_div[11:0] */
2555  *   Preprocessor definitions for the bitfield "lro_ina_ival[9:0]".
2559 /* Register address for bitfield lro_ina_ival[9:0] */
2561 /* Bitmask for bitfield lro_ina_ival[9:0] */
2563 /* Inverted bitmask for bitfield lro_ina_ival[9:0] */
2573  * Preprocessor definitions for the bitfield "lro_max_ival[9:0]".
2577 /* Register address for bitfield lro_max_ival[9:0] */
2579 /* Bitmask for bitfield lro_max_ival[9:0] */
2581 /* Inverted bitmask for bitfield lro_max_ival[9:0] */
2591  * Preprocessor definitions for the bitfield "dca{D}_cpuid[7:0]".
2596 /* Register address for bitfield dca{D}_cpuid[7:0] */
2598 /* Bitmask for bitfield dca{D}_cpuid[7:0] */
2600 /* Inverted bitmask for bitfield dca{D}_cpuid[7:0] */
2610  * Preprocessor definitions for the bitfield "dca{D}_desc_en".
2615 /* Register address for bitfield dca{D}_desc_en */
2617 /* Bitmask for bitfield dca{D}_desc_en */
2619 /* Inverted bitmask for bitfield dca{D}_desc_en */
2629  * Preprocessor definitions for the bitfield "desc{D}_en".
2634 /* Register address for bitfield desc{D}_en */
2636 /* Bitmask for bitfield desc{D}_en */
2638 /* Inverted bitmask for bitfield desc{D}_en */
2648  * Preprocessor definitions for the bitfield "desc{D}_hd[C:0]".
2653 /* Register address for bitfield desc{D}_hd[C:0] */
2655 /* Bitmask for bitfield desc{D}_hd[C:0] */
2657 /* Inverted bitmask for bitfield desc{D}_hd[C:0] */
2665  * Preprocessor definitions for the bitfield "desc{D}_len[9:0]".
2670 /* Register address for bitfield desc{D}_len[9:0] */
2672 /* Bitmask for bitfield desc{D}_len[9:0] */
2674 /* Inverted bitmask for bitfield desc{D}_len[9:0] */
2684  * Preprocessor definitions for the bitfield "desc{D}_wrb_thresh[6:0]".
2689 /* Register address for bitfield desc{D}_wrb_thresh[6:0] */
2692 /* Bitmask for bitfield desc{D}_wrb_thresh[6:0] */
2694 /* Inverted bitmask for bitfield desc{D}_wrb_thresh[6:0] */
2704  * Preprocessor definitions for the bitfield "tdm_int_mod_en".
2708 /* Register address for bitfield tdm_int_mod_en */
2710 /* Bitmask for bitfield tdm_int_mod_en */
2712 /* Inverted bitmask for bitfield tdm_int_mod_en */
2722  * Preprocessor definitions for the bitfield "lso_tcp_flag_mid[B:0]".
2725 /* register address for bitfield lso_tcp_flag_mid[b:0] */
2727 /* bitmask for bitfield lso_tcp_flag_mid[b:0] */
2729 /* inverted bitmask for bitfield lso_tcp_flag_mid[b:0] */
2739  * preprocessor definitions for the bitfield "tx_buf_en".
2743 /* register address for bitfield tx_buf_en */
2745 /* bitmask for bitfield tx_buf_en */
2747 /* inverted bitmask for bitfield tx_buf_en */
2757  * preprocessor definitions for the bitfield "tx_tc_mode".
2761 /* register address for bitfield tx_tc_mode */
2763 /* bitmask for bitfield tx_tc_mode */
2765 /* inverted bitmask for bitfield tx_tc_mode */
2776  * preprocessor definitions for the bitfield "tx{b}_hi_thresh[c:0]".
2781 /* register address for bitfield tx{b}_hi_thresh[c:0] */
2783 /* bitmask for bitfield tx{b}_hi_thresh[c:0] */
2785 /* inverted bitmask for bitfield tx{b}_hi_thresh[c:0] */
2795  * preprocessor definitions for the bitfield "tx{b}_lo_thresh[c:0]".
2800 /* register address for bitfield tx{b}_lo_thresh[c:0] */
2802 /* bitmask for bitfield tx{b}_lo_thresh[c:0] */
2804 /* inverted bitmask for bitfield tx{b}_lo_thresh[c:0] */
2814  * preprocessor definitions for the bitfield "dma_sys_loopback".
2818 /* register address for bitfield dma_sys_loopback */
2820 /* bitmask for bitfield dma_sys_loopback */
2822 /* inverted bitmask for bitfield dma_sys_loopback */
2832  * preprocessor definitions for the bitfield "tx{b}_buf_size[7:0]".
2837 /* register address for bitfield tx{b}_buf_size[7:0] */
2839 /* bitmask for bitfield tx{b}_buf_size[7:0] */
2841 /* inverted bitmask for bitfield tx{b}_buf_size[7:0] */
2851  * preprocessor definitions for the bitfield "tx_scp_ins_en".
2855 /* register address for bitfield tx_scp_ins_en */
2857 /* bitmask for bitfield tx_scp_ins_en */
2859 /* inverted bitmask for bitfield tx_scp_ins_en */
2869  * preprocessor definitions for the bitfield "ipv4_chk_en".
2873 /* register address for bitfield ipv4_chk_en */
2875 /* bitmask for bitfield ipv4_chk_en */
2877 /* inverted bitmask for bitfield ipv4_chk_en */
2887  * preprocessor definitions for the bitfield "l4_chk_en".
2891 /* register address for bitfield l4_chk_en */
2893 /* bitmask for bitfield l4_chk_en */
2895 /* inverted bitmask for bitfield l4_chk_en */
2905  * preprocessor definitions for the bitfield "pkt_sys_loopback".
2909 /* register address for bitfield pkt_sys_loopback */
2911 /* bitmask for bitfield pkt_sys_loopback */
2913 /* inverted bitmask for bitfield pkt_sys_loopback */
2923  * preprocessor definitions for the bitfield "data_tc_arb_mode".
2927 /* register address for bitfield data_tc_arb_mode */
2929 /* bitmask for bitfield data_tc_arb_mode */
2931 /* inverted bitmask for bitfield data_tc_arb_mode */
2941  * preprocessor definitions for the bitfield "desc_rate_ta_rst".
2945 /* register address for bitfield desc_rate_ta_rst */
2947 /* bitmask for bitfield desc_rate_ta_rst */
2949 /* inverted bitmask for bitfield desc_rate_ta_rst */
2959  * preprocessor definitions for the bitfield "desc_rate_limit[a:0]".
2963 /* register address for bitfield desc_rate_limit[a:0] */
2965 /* bitmask for bitfield desc_rate_limit[a:0] */
2967 /* inverted bitmask for bitfield desc_rate_limit[a:0] */
2977  * preprocessor definitions for the bitfield "desc_tc_arb_mode[1:0]".
2981 /* register address for bitfield desc_tc_arb_mode[1:0] */
2983 /* bitmask for bitfield desc_tc_arb_mode[1:0] */
2985 /* inverted bitmask for bitfield desc_tc_arb_mode[1:0] */
2995  * preprocessor definitions for the bitfield "desc_tc{t}_credit_max[b:0]".
3000 /* register address for bitfield desc_tc{t}_credit_max[b:0] */
3002 /* bitmask for bitfield desc_tc{t}_credit_max[b:0] */
3004 /* inverted bitmask for bitfield desc_tc{t}_credit_max[b:0] */
3014  * preprocessor definitions for the bitfield "desc_tc{t}_weight[8:0]".
3019 /* register address for bitfield desc_tc{t}_weight[8:0] */
3021 /* bitmask for bitfield desc_tc{t}_weight[8:0] */
3023 /* inverted bitmask for bitfield desc_tc{t}_weight[8:0] */
3033  * preprocessor definitions for the bitfield "desc_vm_arb_mode".
3037 /* register address for bitfield desc_vm_arb_mode */
3039 /* bitmask for bitfield desc_vm_arb_mode */
3041 /* inverted bitmask for bitfield desc_vm_arb_mode */
3051  * preprocessor definitions for the bitfield "data_tc{t}_credit_max[b:0]".
3056 /* register address for bitfield data_tc{t}_credit_max[b:0] */
3058 /* bitmask for bitfield data_tc{t}_credit_max[b:0] */
3060 /* inverted bitmask for bitfield data_tc{t}_credit_max[b:0] */
3070  * preprocessor definitions for the bitfield "data_tc{t}_weight[8:0]".
3075 /* register address for bitfield data_tc{t}_weight[8:0] */
3077 /* bitmask for bitfield data_tc{t}_weight[8:0] */
3079 /* inverted bitmask for bitfield data_tc{t}_weight[8:0] */
3089  * preprocessor definitions for the bitfield "reg_res_dsbl".
3093 /* register address for bitfield reg_res_dsbl */
3095 /* bitmask for bitfield reg_res_dsbl */
3097 /* inverted bitmask for bitfield reg_res_dsbl */
3107  * preprocessor definitions for the bitfield "register access busy".
3111 /* register address for bitfield register access busy */
3113 /* bitmask for bitfield register access busy */
3115 /* inverted bitmask for bitfield register access busy */
3123  * preprocessor definitions for the bitfield "msm register address[7:0]".
3127 /* register address for bitfield msm register address[7:0] */
3129 /* bitmask for bitfield msm register address[7:0] */
3131 /* inverted bitmask for bitfield msm register address[7:0] */
3141  * preprocessor definitions for the bitfield "register read strobe".
3145 /* register address for bitfield register read strobe */
3147 /* bitmask for bitfield register read strobe */
3149 /* inverted bitmask for bitfield register read strobe */
3159  * preprocessor definitions for the bitfield "msm register read data[31:0]".
3163 /* register address for bitfield msm register read data[31:0] */
3165 /* bitmask for bitfield msm register read data[31:0] */
3167 /* inverted bitmask for bitfield msm register read data[31:0] */
3175  * preprocessor definitions for the bitfield "msm register write data[31:0]".
3179 /* register address for bitfield msm register write data[31:0] */
3181 /* bitmask for bitfield msm register write data[31:0] */
3183 /* inverted bitmask for bitfield msm register write data[31:0] */
3193  * preprocessor definitions for the bitfield "register write strobe".
3197 /* register address for bitfield register write strobe */
3199 /* bitmask for bitfield register write strobe */
3201 /* inverted bitmask for bitfield register write strobe */
3211  * preprocessor definitions for the bitfield "soft reset".
3215 /* register address for bitfield soft reset */
3217 /* bitmask for bitfield soft reset */
3219 /* inverted bitmask for bitfield soft reset */
3229  * preprocessor definitions for the bitfield "register reset disable".
3233 /* register address for bitfield register reset disable */
3235 /* bitmask for bitfield register reset disable */
3237 /* inverted bitmask for bitfield register reset disable */
3254  * Preprocessor definitions for TX Interrupt Moderation Control Register
3262  * preprocessor definitions for the bitfield "reg_res_dsbl".
3266 /* register address for bitfield reg_res_dsbl */
3268 /* bitmask for bitfield reg_res_dsbl */
3270 /* inverted bitmask for bitfield reg_res_dsbl */
3287 *   Preprocessor definitions for Global Standard Control 1
3295 *   Preprocessor definitions for Global Control 2
3303 *   Preprocessor definitions for Global Daisy Chain Status 1