Lines Matching +full:rx +full:- +full:threshold

3  * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
134 /* get rx dma good octet counter lsw */
137 /* get rx dma good packet counter lsw */
146 /* get rx dma good octet counter msw */
149 /* get rx dma good packet counter msw */
158 /* get  rx lro coalesced packet count lsw */
161 /* get msm rx errors counter register */
164 /* get msm rx unicast frames counter register */
167 /* get msm rx multicast frames counter register */
170 /* get msm rx broadcast frames counter register */
173 /* get msm rx broadcast octets counter register 1 */
176 /* get msm rx unicast octets counter register 0 */
179 /* get rx dma statistics counter 7 */
207 …egisterResetDisable 1 = Disable the S/W reset to MAC-PHY registers, 0 = Enable the S/W reset to MA…
213 *   \return 1 = Disable the S/W reset to MAC-PHY registers, 0 = Enable the S/W reset to MAC-PHY reg…
225 /* set interrupt mapping enable rx */
226 void itr_irq_map_en_rx_set(struct aq_hw *aq_hw, u32 irq_map_en_rx, u32 rx);
231 /* set interrupt mapping rx */
232 void itr_irq_map_rx_set(struct aq_hw *aq_hw, u32 irq_map_rx, u32 rx);
295 /* set rx dca enable */
298 /* set rx dca mode */
301 /* set rx descriptor data buffer size */
306 /* set rx descriptor dca enable */
310 /* set rx descriptor enable */
314 /* set rx descriptor header splitting */
319 /* get rx descriptor head pointer */
322 /* set rx descriptor length */
326 /* set rx descriptor write-back interrupt enable */
330 /* set rx header dca enable */
334 /* set rx payload dca enable */
337 /* set rx descriptor header buffer size */
342 /* set rx descriptor reset */
363 /* set rx dma descriptor base address lsw */
368 /* set rx dma descriptor base address msw */
373 /* get rx dma descriptor status register */
376 /* set rx dma descriptor tail pointer register */
380 /* get rx dma descriptor tail pointer register */
383 /* set rx filter multicast filter mask register */
387 /* set rx filter multicast filter register */
391 /* set rx filter rss control register 1 */
395 /* Set RX Filter Control Register 2 */
398 /* Set RX Interrupt Moderation Control Register */
446 /* set rx traffic class mode */
450 /* set rx buffer enable */
453 /* set rx buffer high threshold (per tc) */
458 /* set rx buffer low threshold (per tc) */
463 /* set rx flow control mode */
466 /* set rx packet buffer size (per tc) */
471 /* set rx xoff enable (per tc) */
477 /* set l2 broadcast count threshold */
518 /* set user-priority tc mapping */
585 /* Set VLAN RX queue assignment enable */
589 /* Set VLAN RX queue */
597 /* set  ethertype user-priority enable */
602 /* set  ethertype rx queue enable */
607 /* set ethertype rx queue */
611 /* set ethertype user-priority */
651 /* set L3/L4 rx queue enable */
660 /* set L3/L4 rx queue */
701 /* set  ethertype user-priority enable */
705 /* set  ethertype rx queue enable */
709 /* set ethertype rx queue */
713 /* set ethertype user-priority */
752 /* set L3/L4 rx queue enable */
761 /* set L3/L4 rx queue */
779 /* set rx descriptor vlan stripping */
824 /* rx */
826 /* set rx register reset disable */
857 /* set tx descriptor write-back interrupt enable */
861 /* set tx descriptor write-back threshold */
891 /* set tx buffer high threshold (per tc) */
896 /* set tx buffer low threshold (per tc) */
908 /* toggle rdm rx dma descriptor cache init */
1031 /* clear command for filter l3-l4 */
1048 /* set command for filter l3-l4 */
1089 /* Set VLAN RX queue assignment enable */
1093 /* Set VLAN RX queue */
1101 /* set  ethertype user-priority enable */
1106 /* set  ethertype rx queue enable */
1111 /* set ethertype rx queue */
1115 /* set ethertype user-priority */
1155 /* set L3/L4 rx queue enable */
1164 /* set L3/L4 rx queue */