Lines Matching +full:no +full:- +full:temp +full:- +full:support
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
6 * Copyright (c) 2009-2012 Jung-uk Kim <jkim@FreeBSD.org>
8 * Copyright (c) 2017-2020 Conrad Meyer <cem@FreeBSD.org>. All rights reserved.
22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
33 * Driver for the AMD CPU on-die thermal sensors.
77 NUM_CCDS = CCD_MAX - CCD_BASE + 1,
85 #define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */
86 #define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */
99 * when adding support for new devices.
125 * 0xFC register is only valid on the D18F3 PCI device; SMN temp
151 * Reported Temperature Control Register, family 0Fh-15h (some models), 16h.
171 * According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register
172 * provide the current temp. bit 19, when clear, means the temp is reported in
174 * to -49..206C.
179 * Bits 16-17, when set, mean that CUR_TMP is read-write. When it is, the
283 if (device_find_child(parent, "amdtemp", -1) != NULL) in amdtemp_identify()
324 device_set_desc(dev, "AMD CPU On-Die Thermal Sensors"); in amdtemp_probe()
356 * revision multi-socket system where the attach thread is potentially in amdtemp_attach()
366 if (product->amdtemp_has_cpuid && (family > 0x0f || in amdtemp_attach()
379 * - ThermSenseCoreSel in amdtemp_attach()
381 * Revision F & G: 0 - Core1, 1 - Core0 in amdtemp_attach()
382 * Other: 0 - Core0, 1 - Core1 in amdtemp_attach()
384 * - CurTmp in amdtemp_attach()
386 * Revision G: bits 23-14 in amdtemp_attach()
387 * Other: bits 23-16 in amdtemp_attach()
397 * XXX According to Linux, CurTmp starts at -28C on in amdtemp_attach()
402 sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP; in amdtemp_attach()
413 sc->sc_flags |= in amdtemp_attach()
420 sc->sc_flags |= in amdtemp_attach()
424 sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET; in amdtemp_attach()
426 sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT; in amdtemp_attach()
432 sc->sc_ntemps = 2; in amdtemp_attach()
434 sc->sc_gettemp = amdtemp_gettemp0f; in amdtemp_attach()
440 * http://support.amd.com/us/Processor_TechDocs/41322.pdf in amdtemp_attach()
454 /* XXX 00100F42h (RB-C2) exists in both formats. */ in amdtemp_attach()
464 sc->sc_ntemps = 1; in amdtemp_attach()
468 * from 17h and the decoding matches other 10h-15h models, in amdtemp_attach()
472 sc->sc_gettemp = amdtemp_gettemp15hm60h; in amdtemp_attach()
475 sc->sc_gettemp = amdtemp_gettemp; in amdtemp_attach()
479 sc->sc_ntemps = 1; in amdtemp_attach()
480 sc->sc_gettemp = amdtemp_gettemp17h; in amdtemp_attach()
489 sc->sc_smn = device_find_child( in amdtemp_attach()
490 device_get_parent(dev), "amdsmn", -1); in amdtemp_attach()
491 if (sc->sc_smn == NULL) { in amdtemp_attach()
493 device_printf(dev, "No SMN device found\n"); in amdtemp_attach()
499 sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ? in amdtemp_attach()
501 if (sc->sc_ncores > MAXCPU) in amdtemp_attach()
504 mtx_init(&sc->sc_lock, "amdtemp", NULL, MTX_DEF); in amdtemp_attach()
510 sc->sc_ncores, in amdtemp_attach()
511 sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1); in amdtemp_attach()
518 TUNABLE_INT_FETCH(tn, &sc->sc_offset); in amdtemp_attach()
523 "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0, in amdtemp_attach()
536 sc->sc_temp_base = AMDTEMP_17H_CCD_TMP_BASE; in amdtemp_attach()
542 else if (sc->sc_ntemps > 1) { in amdtemp_attach()
550 if (sc->sc_ncores > 1) { in amdtemp_attach()
578 sc->sc_ich.ich_func = amdtemp_intrhook; in amdtemp_attach()
579 sc->sc_ich.ich_arg = dev; in amdtemp_attach()
580 if (config_intrhook_establish(&sc->sc_ich) != 0) { in amdtemp_attach()
606 for (i = 0; i < sc->sc_ncores; i++) { in amdtemp_intrhook()
607 if (sc->sc_sysctl_cpu[i] != NULL) in amdtemp_intrhook()
610 device_get_unit(dev) * sc->sc_ncores + i); in amdtemp_intrhook()
614 sensor = sc->sc_ntemps > 1 ? in amdtemp_intrhook()
616 sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx, in amdtemp_intrhook()
624 if (sc->sc_ich.ich_arg != NULL) in amdtemp_intrhook()
625 config_intrhook_disestablish(&sc->sc_ich); in amdtemp_intrhook()
634 for (i = 0; i < sc->sc_ncores; i++) in amdtemp_detach()
635 if (sc->sc_sysctl_cpu[i] != NULL) in amdtemp_detach()
636 sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0); in amdtemp_detach()
640 mtx_destroy(&sc->sc_lock); in amdtemp_detach()
650 int32_t auxtemp[2], temp; in amdtemp_sysctl() local
655 auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0); in amdtemp_sysctl()
656 auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1); in amdtemp_sysctl()
657 temp = imax(auxtemp[0], auxtemp[1]); in amdtemp_sysctl()
660 auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0); in amdtemp_sysctl()
661 auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1); in amdtemp_sysctl()
662 temp = imax(auxtemp[0], auxtemp[1]); in amdtemp_sysctl()
665 temp = sc->sc_gettemp(dev, sensor); in amdtemp_sysctl()
668 error = sysctl_handle_int(oidp, &temp, 0, req); in amdtemp_sysctl()
679 uint32_t mask, offset, temp; in amdtemp_gettemp0f() local
681 mtx_lock(&sc->sc_lock); in amdtemp_gettemp0f()
684 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1); in amdtemp_gettemp0f()
685 temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR); in amdtemp_gettemp0f()
688 temp |= AMDTEMP_TTSR_SELSENSOR; in amdtemp_gettemp0f()
692 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0) in amdtemp_gettemp0f()
693 temp |= AMDTEMP_TTSR_SELCORE; in amdtemp_gettemp0f()
696 temp |= AMDTEMP_TTSR_SELSENSOR; in amdtemp_gettemp0f()
700 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0) in amdtemp_gettemp0f()
701 temp |= AMDTEMP_TTSR_SELCORE; in amdtemp_gettemp0f()
706 pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1); in amdtemp_gettemp0f()
708 mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc; in amdtemp_gettemp0f()
709 offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49; in amdtemp_gettemp0f()
710 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4); in amdtemp_gettemp0f()
711 temp = ((temp >> 14) & mask) * 5 / 2; in amdtemp_gettemp0f()
712 temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10; in amdtemp_gettemp0f()
714 mtx_unlock(&sc->sc_lock); in amdtemp_gettemp0f()
715 return (temp); in amdtemp_gettemp0f()
721 uint32_t temp; in amdtemp_decode_fam10h_to_17h() local
724 temp = (val & AMDTEMP_REPTMP10H_CURTMP_MASK) * 5 / 4; in amdtemp_decode_fam10h_to_17h()
727 temp -= AMDTEMP_CURTMP_RANGE_ADJUST; in amdtemp_decode_fam10h_to_17h()
729 temp += AMDTEMP_ZERO_C_TO_K + sc_offset * 10; in amdtemp_decode_fam10h_to_17h()
730 return (temp); in amdtemp_decode_fam10h_to_17h()
766 uint32_t temp; in amdtemp_gettemp() local
768 temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4); in amdtemp_gettemp()
769 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, temp)); in amdtemp_gettemp()
779 error = amdsmn_read(sc->sc_smn, AMDTEMP_15H_M60H_REPTMP_CTRL, &val); in amdtemp_gettemp15hm60h()
781 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, val)); in amdtemp_gettemp15hm60h()
794 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val); in amdtemp_gettemp17h()
796 return (amdtemp_decode_fam17h_tctl(sc->sc_offset, val)); in amdtemp_gettemp17h()
799 error = amdsmn_read(sc->sc_smn, sc->sc_temp_base + in amdtemp_gettemp17h()
800 (((int)sensor - CCD_BASE) * sizeof(val)), &val); in amdtemp_gettemp17h()
804 return (amdtemp_decode_fam10h_to_17h(sc->sc_offset, val, true)); in amdtemp_gettemp17h()
820 error = amdsmn_read(sc->sc_smn, sc->sc_temp_base + in amdtemp_probe_ccd_sensors()
875 sc->sc_temp_base = AMDTEMP_ZEN4_10H_CCD_TMP_BASE; in amdtemp_probe_ccd_sensors19h()
882 sc->sc_temp_base = AMDTEMP_ZEN4_CCD_TMP_BASE; in amdtemp_probe_ccd_sensors19h()