84 #define	AMDTEMP_FLAG_CS_SWAP	0x01	/* ThermSenseCoreSel is inverted. */
85 #define	AMDTEMP_FLAG_CT_10BIT	0x02	/* CurTmp is 10-bit wide. */
86 #define	AMDTEMP_FLAG_ALT_OFFSET	0x04	/* CurTmp starts at -28C. */
101 #define	VENDORID_AMD		0x1022
102 #define	DEVICEID_AMD_MISC0F	0x1103
103 #define	DEVICEID_AMD_MISC10	0x1203
104 #define	DEVICEID_AMD_MISC11	0x1303
105 #define	DEVICEID_AMD_MISC14	0x1703
106 #define	DEVICEID_AMD_MISC15	0x1603
107 #define	DEVICEID_AMD_MISC15_M10H	0x1403
108 #define	DEVICEID_AMD_MISC15_M30H	0x141d
109 #define	DEVICEID_AMD_MISC15_M60H_ROOT	0x1576
110 #define	DEVICEID_AMD_MISC16	0x1533
111 #define	DEVICEID_AMD_MISC16_M30H	0x1583
112 #define	DEVICEID_AMD_HOSTB17H_ROOT	0x1450
113 #define	DEVICEID_AMD_HOSTB17H_M10H_ROOT	0x15d0
114 #define	DEVICEID_AMD_HOSTB17H_M30H_ROOT	0x1480	/* Also M70H, F19H M00H/M20H */
115 #define	DEVICEID_AMD_HOSTB17H_M60H_ROOT	0x1630	/* Also F19H M50H */
116 #define	DEVICEID_AMD_HOSTB19H_M10H_ROOT	0x14a4
117 #define	DEVICEID_AMD_HOSTB19H_M40H_ROOT	0x14b5
118 #define	DEVICEID_AMD_HOSTB19H_M60H_ROOT	0x14d8	/* Also F1AH M40H */
119 #define	DEVICEID_AMD_HOSTB19H_M70H_ROOT	0x14e8
120 #define	DEVICEID_AMD_HOSTB1AH_M00H_ROOT	0x153a
121 #define	DEVICEID_AMD_HOSTB1AH_M20H_ROOT	0x1507
122 #define	DEVICEID_AMD_HOSTB1AH_M60H_ROOT	0x1122
128 	 * 0xFC register is only valid on the D18F3 PCI device; SMN temp
157  * Reported Temperature Control Register, family 0Fh-15h (some models), 16h.
159 #define	AMDTEMP_REPTMP_CTRL	0xa4
161 #define	AMDTEMP_REPTMP10H_CURTMP_MASK	0x7ff
163 #define	AMDTEMP_REPTMP10H_TJSEL_MASK	0x3
172 #define	AMDTEMP_15H_M60H_REPTMP_CTRL	0xd8200ca4
179  * a range 0.."225C" (probable typo for 255C), and when set changes the range
182 #define	AMDTEMP_17H_CUR_TMP		0x59800
193  * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to
196 #define	AMDTEMP_17H_CCD_TMP_BASE	0x59954
199 #define	AMDTEMP_ZEN4_10H_CCD_TMP_BASE	0x59b00
200 #define	AMDTEMP_ZEN4_CCD_TMP_BASE	0x59b08
208  * Thermaltrip Status Register (Family 0Fh only)
210 #define	AMDTEMP_THERMTP_STAT	0xe4
211 #define	AMDTEMP_TTSR_SELCORE	0x04
212 #define	AMDTEMP_TTSR_SELSENSOR	0x40
217 #define	AMDTEMP_DRAM_CONF_HIGH	0x94	/* Function 2 */
218 #define	AMDTEMP_DRAM_MODE_DDR3	0x0100
223 #define	AMDTEMP_CPUID		0xfc
273 	for (i = 0; i < nitems(amdtemp_products); i++) {  in amdtemp_match()
305 	if (resource_disabled("amdtemp", 0)) {  in amdtemp_probe()
321 	case 0x0f:  in amdtemp_probe()
322 		if ((model == 0x04 && stepping == 0) ||  in amdtemp_probe()
323 		    (model == 0x05 && stepping <= 1)) {  in amdtemp_probe()
331 	case 0x10:  in amdtemp_probe()
332 	case 0x11:  in amdtemp_probe()
333 	case 0x12:  in amdtemp_probe()
334 	case 0x14:  in amdtemp_probe()
335 	case 0x15:  in amdtemp_probe()
336 	case 0x16:  in amdtemp_probe()
337 	case 0x17:  in amdtemp_probe()
338 	case 0x19:  in amdtemp_probe()
339 	case 0x1a:  in amdtemp_probe()
365 	erratum319 = 0;  in amdtemp_attach()
384 	 * The ancient 0x0F family of devices only supports this register from  in amdtemp_attach()
387 	if (product->amdtemp_has_cpuid && (family > 0x0f ||  in amdtemp_attach()
388 	    (family == 0x0f && model >= 0x40))) {  in amdtemp_attach()
396 	case 0x0f:  in amdtemp_attach()
402 		 * Revision F & G:	0 - Core1, 1 - Core0  in amdtemp_attach()
403 		 * Other:		0 - Core0, 1 - Core1  in amdtemp_attach()
422 		if (model >= 0x40)  in amdtemp_attach()
424 		if (model >= 0x60 && model != 0xc1) {  in amdtemp_attach()
425 			do_cpuid(0x80000001, regs);  in amdtemp_attach()
426 			bid = (regs[1] >> 9) & 0x1f;  in amdtemp_attach()
428 			case 0x68: /* Socket S1g1 */  in amdtemp_attach()
429 			case 0x6c:  in amdtemp_attach()
430 			case 0x7c:  in amdtemp_attach()
432 			case 0x6b: /* Socket AM2 and ASB1 (2 cores) */  in amdtemp_attach()
433 				if (bid != 0x0b && bid != 0x0c)  in amdtemp_attach()
437 			case 0x6f: /* Socket AM2 and ASB1 (1 core) */  in amdtemp_attach()
438 			case 0x7f:  in amdtemp_attach()
439 				if (bid != 0x07 && bid != 0x09 &&  in amdtemp_attach()
440 				    bid != 0x0c)  in amdtemp_attach()
457 	case 0x10:  in amdtemp_attach()
463 		do_cpuid(0x80000001, regs);  in amdtemp_attach()
464 		switch ((regs[1] >> 28) & 0xf) {  in amdtemp_attach()
465 		case 0:	/* Socket F */  in amdtemp_attach()
472 			    AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 ||  in amdtemp_attach()
473 			    (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3))  in amdtemp_attach()
480 	case 0x11:  in amdtemp_attach()
481 	case 0x12:  in amdtemp_attach()
482 	case 0x14:  in amdtemp_attach()
483 	case 0x15:  in amdtemp_attach()
484 	case 0x16:  in amdtemp_attach()
492 		if (family == 0x15 && model >= 0x60) {  in amdtemp_attach()
498 	case 0x17:  in amdtemp_attach()
499 	case 0x19:  in amdtemp_attach()
500 	case 0x1a:  in amdtemp_attach()
521 	sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ?  in amdtemp_attach()
545 	    "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0,  in amdtemp_attach()
549 	    "core0", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "Core 0");  in amdtemp_attach()
556 	    "Core 0 / Sensor 0 temperature");  in amdtemp_attach()
560 	if (family == 0x17)  in amdtemp_attach()
562 	else if (family == 0x19)  in amdtemp_attach()
564 	else if (family == 0x1a)  in amdtemp_attach()
572 		    "Core 0 / Sensor 1 temperature");  in amdtemp_attach()
578 			    0, "Core 1");  in amdtemp_attach()
585 			    "Core 1 / Sensor 0 temperature");  in amdtemp_attach()
604 	if (config_intrhook_establish(&sc->sc_ich) != 0) {  in amdtemp_attach()
609 	return (0);  in amdtemp_attach()
627 	nexus = device_find_child(root_bus, "nexus", 0);  in amdtemp_intrhook()
628 	acpi = device_find_child(nexus, "acpi", 0);  in amdtemp_intrhook()
630 	for (i = 0; i < sc->sc_ncores; i++) {  in amdtemp_intrhook()
639 			    (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0;  in amdtemp_intrhook()
658 	for (i = 0; i < sc->sc_ncores; i++)  in amdtemp_detach()
660 			sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0);  in amdtemp_detach()
665 	return (0);  in amdtemp_detach()
679 		auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0);  in amdtemp_sysctl()
681 		temp = imax(auxtemp[0], auxtemp[1]);  in amdtemp_sysctl()
684 		auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0);  in amdtemp_sysctl()
686 		temp = imax(auxtemp[0], auxtemp[1]);  in amdtemp_sysctl()
692 	error = sysctl_handle_int(oidp, &temp, 0, req);  in amdtemp_sysctl()
716 		if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0)  in amdtemp_gettemp0f()
724 		if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0)  in amdtemp_gettemp0f()
732 	mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc;  in amdtemp_gettemp0f()
733 	offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49;  in amdtemp_gettemp0f()
767 	minus49 = (CPUID_TO_FAMILY(cpu_id) >= 0x15 &&  in amdtemp_decode_fam10h_to_16h()
769 	    AMDTEMP_REPTMP10H_TJSEL_MASK) == 0x3);  in amdtemp_decode_fam10h_to_16h()
780 	minus49 = ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0)  in amdtemp_decode_fam17h_tctl()
804 	KASSERT(error == 0, ("amdsmn_read"));  in amdtemp_gettemp15hm60h()
819 		KASSERT(error == 0, ("amdsmn_read"));  in amdtemp_gettemp17h()
825 		KASSERT(error == 0, ("amdsmn_read2"));  in amdtemp_gettemp17h()
826 		KASSERT((val & AMDTEMP_17H_CCD_TMP_VALID) != 0,  in amdtemp_gettemp17h()
843 	for (i = 0; i < maxreg; i++) {  in amdtemp_probe_ccd_sensors()
846 		if (error != 0)  in amdtemp_probe_ccd_sensors()
848 		if ((val & AMDTEMP_17H_CCD_TMP_VALID) == 0)  in amdtemp_probe_ccd_sensors()
868 	case 0x00 ... 0x2f: /* Zen1, Zen+ */  in amdtemp_probe_ccd_sensors17h()
871 	case 0x30 ... 0x3f: /* Zen2 TR (Castle Peak)/EPYC (Rome) */  in amdtemp_probe_ccd_sensors17h()
872 	case 0x60 ... 0x7f: /* Zen2 Ryzen (Renoir APU, Matisse) */  in amdtemp_probe_ccd_sensors17h()
873 	case 0x90 ... 0x9f: /* Zen2 Ryzen (Van Gogh APU) */  in amdtemp_probe_ccd_sensors17h()
893 	case 0x00 ... 0x0f: /* Zen3 EPYC "Milan" */  in amdtemp_probe_ccd_sensors19h()
894 	case 0x20 ... 0x2f: /* Zen3 Ryzen "Vermeer" */  in amdtemp_probe_ccd_sensors19h()
895 	case 0x50 ... 0x5f: /* Zen3 Ryzen "Cezanne" */  in amdtemp_probe_ccd_sensors19h()
899 	case 0x10 ... 0x1f: /* Zen4 EPYC "Genoa" */  in amdtemp_probe_ccd_sensors19h()
904 	case 0x40 ... 0x4f: /* Zen3+ Ryzen "Rembrandt" */  in amdtemp_probe_ccd_sensors19h()
905 	case 0x60 ... 0x6f: /* Zen4 Ryzen "Raphael" */  in amdtemp_probe_ccd_sensors19h()
906 	case 0x70 ... 0x7f: /* Zen4 Ryzen "Phoenix" */  in amdtemp_probe_ccd_sensors19h()
927 	case 0x00 ... 0x2f: /* Zen5 EPYC "Turin" */  in amdtemp_probe_ccd_sensors1ah()
928 	case 0x40 ... 0x4f: /* Zen5 Ryzen "Granite Ridge" */  in amdtemp_probe_ccd_sensors1ah()
929 	case 0x60 ... 0x7f: /* ??? */  in amdtemp_probe_ccd_sensors1ah()