Lines Matching +full:0 +full:x0000003c
36 #define VENDORID_ATHEROS 0x1969
41 #define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */
42 #define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */
43 #define DEVICEID_ATHEROS_AR8151 0x1073 /* L1D V1.0 */
44 #define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */
45 #define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */
46 #define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */
47 #define DEVICEID_ATHEROS_AR8161 0x1091
48 #define DEVICEID_ATHEROS_AR8162 0x1090
49 #define DEVICEID_ATHEROS_AR8171 0x10A1
50 #define DEVICEID_ATHEROS_AR8172 0x10A0
51 #define DEVICEID_ATHEROS_E2200 0xE091
52 #define DEVICEID_ATHEROS_E2400 0xE0A1
53 #define DEVICEID_ATHEROS_E2500 0xE0B1
55 #define ATHEROS_AR8152_B_V10 0xC0
56 #define ATHEROS_AR8152_B_V11 0xC1
61 #define AR816X_REV_A0 0
69 /* 0x0000 - 0x02FF : PCIe configuration space */
71 #define ALC_PEX_UNC_ERR_SEV 0x10C
72 #define PEX_UNC_ERR_SEV_TRN 0x00000001
73 #define PEX_UNC_ERR_SEV_DLP 0x00000010
74 #define PEX_UNC_ERR_SEV_PSN_TLP 0x00001000
75 #define PEX_UNC_ERR_SEV_FCP 0x00002000
76 #define PEX_UNC_ERR_SEV_CPL_TO 0x00004000
77 #define PEX_UNC_ERR_SEV_CA 0x00008000
78 #define PEX_UNC_ERR_SEV_UC 0x00010000
79 #define PEX_UNC_ERR_SEV_ROV 0x00020000
80 #define PEX_UNC_ERR_SEV_MLFP 0x00040000
81 #define PEX_UNC_ERR_SEV_ECRC 0x00080000
82 #define PEX_UNC_ERR_SEV_UR 0x00100000
84 #define ALC_EEPROM_LD 0x204 /* AR816x */
85 #define EEPROM_LD_START 0x00000001
86 #define EEPROM_LD_IDLE 0x00000010
87 #define EEPROM_LD_DONE 0x00000000
88 #define EEPROM_LD_PROGRESS 0x00000020
89 #define EEPROM_LD_EXIST 0x00000100
90 #define EEPROM_LD_EEPROM_EXIST 0x00000200
91 #define EEPROM_LD_FLASH_EXIST 0x00000400
92 #define EEPROM_LD_FLASH_END_ADDR_MASK 0x03FF0000
95 #define ALC_TWSI_CFG 0x218
96 #define TWSI_CFG_SW_LD_START 0x00000800
97 #define TWSI_CFG_HW_LD_START 0x00001000
98 #define TWSI_CFG_LD_EXIST 0x00400000
100 #define ALC_SLD 0x218 /* AR816x */
101 #define SLD_START 0x00000800
102 #define SLD_PROGRESS 0x00001000
103 #define SLD_IDLE 0x00002000
104 #define SLD_SLVADDR_MASK 0x007F0000
105 #define SLD_EXIST 0x00800000
106 #define SLD_FREQ_MASK 0x03000000
107 #define SLD_FREQ_100K 0x00000000
108 #define SLD_FREQ_200K 0x01000000
109 #define SLD_FREQ_300K 0x02000000
110 #define SLD_FREQ_400K 0x03000000
112 #define ALC_PCIE_PHYMISC 0x1000
113 #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004
115 #define ALC_PCIE_PHYMISC2 0x1004
116 #define PCIE_PHYMISC2_SERDES_CDR_MASK 0x00030000
117 #define PCIE_PHYMISC2_SERDES_TH_MASK 0x000C0000
121 #define ALC_PDLL_TRNS1 0x1104
122 #define PDLL_TRNS1_D3PLLOFF_ENB 0x00000800
124 #define ALC_TWSI_DEBUG 0x1108
125 #define TWSI_DEBUG_DEV_EXIST 0x20000000
127 #define ALC_EEPROM_CFG 0x12C0
128 #define EEPROM_CFG_DATA_HI_MASK 0x0000FFFF
129 #define EEPROM_CFG_ADDR_MASK 0x03FF0000
130 #define EEPROM_CFG_ACK 0x40000000
131 #define EEPROM_CFG_RW 0x80000000
132 #define EEPROM_CFG_DATA_HI_SHIFT 0
135 #define ALC_EEPROM_DATA_LO 0x12C4
137 #define ALC_OPT_CFG 0x12F0
138 #define OPT_CFG_CLK_ENB 0x00000002
140 #define ALC_PM_CFG 0x12F8
141 #define PM_CFG_SERDES_ENB 0x00000001
142 #define PM_CFG_RBER_ENB 0x00000002
143 #define PM_CFG_CLK_REQ_ENB 0x00000004
144 #define PM_CFG_ASPM_L1_ENB 0x00000008
145 #define PM_CFG_SERDES_L1_ENB 0x00000010
146 #define PM_CFG_SERDES_PLL_L1_ENB 0x00000020
147 #define PM_CFG_SERDES_PD_EX_L1 0x00000040
148 #define PM_CFG_SERDES_BUDS_RX_L1_ENB 0x00000080
149 #define PM_CFG_L0S_ENTRY_TIMER_MASK 0x00000F00
150 #define PM_CFG_RX_L1_AFTER_L0S 0x00000800
151 #define PM_CFG_ASPM_L0S_ENB 0x00001000
152 #define PM_CFG_CLK_SWH_L1 0x00002000
153 #define PM_CFG_CLK_PWM_VER1_1 0x00004000
154 #define PM_CFG_PCIE_RECV 0x00008000
155 #define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000
156 #define PM_CFG_L1_ENTRY_TIMER_816X_MASK 0x00070000
157 #define PM_CFG_TX_L1_AFTER_L0S 0x00080000
158 #define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000
159 #define PM_CFG_LCKDET_TIMER_MASK 0x0F000000
160 #define PM_CFG_EN_BUFS_RX_L0S 0x10000000
161 #define PM_CFG_SA_DLY_ENB 0x20000000
162 #define PM_CFG_MAC_ASPM_CHK 0x40000000
163 #define PM_CFG_HOTRST 0x80000000
176 #define ALC_LTSSM_ID_CFG 0x12FC
177 #define LTSSM_ID_WRO_ENB 0x00001000
179 #define ALC_MASTER_CFG 0x1400
180 #define MASTER_RESET 0x00000001
181 #define MASTER_TEST_MODE_MASK 0x0000000C
182 #define MASTER_BERT_START 0x00000010
183 #define MASTER_WAKEN_25M 0x00000020
184 #define MASTER_OOB_DIS_OFF 0x00000040
185 #define MASTER_SA_TIMER_ENB 0x00000080
186 #define MASTER_MTIMER_ENB 0x00000100
187 #define MASTER_MANUAL_INTR_ENB 0x00000200
188 #define MASTER_IM_TX_TIMER_ENB 0x00000400
189 #define MASTER_IM_RX_TIMER_ENB 0x00000800
190 #define MASTER_CLK_SEL_DIS 0x00001000
191 #define MASTER_CLK_SWH_MODE 0x00002000
192 #define MASTER_INTR_RD_CLR 0x00004000
193 #define MASTER_CHIP_REV_MASK 0x00FF0000
194 #define MASTER_CHIP_ID_MASK 0x7F000000
195 #define MASTER_OTP_SEL 0x80000000
204 #define ALC_MANUAL_TIMER 0x1404
206 #define ALC_IM_TIMER 0x1408
207 #define IM_TIMER_TX_MASK 0x0000FFFF
208 #define IM_TIMER_RX_MASK 0xFFFF0000
209 #define IM_TIMER_TX_SHIFT 0
211 #define ALC_IM_TIMER_MIN 0
224 #define ALC_GPHY_CFG 0x140C /* 16 bits, 32 bits on AR816x */
225 #define GPHY_CFG_EXT_RESET 0x0001
226 #define GPHY_CFG_RTL_MODE 0x0002
227 #define GPHY_CFG_LED_MODE 0x0004
228 #define GPHY_CFG_ANEG_NOW 0x0008
229 #define GPHY_CFG_RECV_ANEG 0x0010
230 #define GPHY_CFG_GATE_25M_ENB 0x0020
231 #define GPHY_CFG_LPW_EXIT 0x0040
232 #define GPHY_CFG_PHY_IDDQ 0x0080
233 #define GPHY_CFG_PHY_IDDQ_DIS 0x0100
234 #define GPHY_CFG_PCLK_SEL_DIS 0x0200
235 #define GPHY_CFG_HIB_EN 0x0400
236 #define GPHY_CFG_HIB_PULSE 0x0800
237 #define GPHY_CFG_SEL_ANA_RESET 0x1000
238 #define GPHY_CFG_PHY_PLL_ON 0x2000
239 #define GPHY_CFG_PWDOWN_HW 0x4000
240 #define GPHY_CFG_PHY_PLL_BYPASS 0x8000
241 #define GPHY_CFG_100AB_ENB 0x00020000
243 #define ALC_IDLE_STATUS 0x1410
244 #define IDLE_STATUS_RXMAC 0x00000001
245 #define IDLE_STATUS_TXMAC 0x00000002
246 #define IDLE_STATUS_RXQ 0x00000004
247 #define IDLE_STATUS_TXQ 0x00000008
248 #define IDLE_STATUS_DMARD 0x00000010
249 #define IDLE_STATUS_DMAWR 0x00000020
250 #define IDLE_STATUS_SMB 0x00000040
251 #define IDLE_STATUS_CMB 0x00000080
253 #define ALC_MDIO 0x1414
254 #define MDIO_DATA_MASK 0x0000FFFF
255 #define MDIO_REG_ADDR_MASK 0x001F0000
256 #define MDIO_OP_READ 0x00200000
257 #define MDIO_OP_WRITE 0x00000000
258 #define MDIO_SUP_PREAMBLE 0x00400000
259 #define MDIO_OP_EXECUTE 0x00800000
260 #define MDIO_CLK_25_4 0x00000000
261 #define MDIO_CLK_25_6 0x02000000
262 #define MDIO_CLK_25_8 0x03000000
263 #define MDIO_CLK_25_10 0x04000000
264 #define MDIO_CLK_25_14 0x05000000
265 #define MDIO_CLK_25_20 0x06000000
266 #define MDIO_CLK_25_128 0x07000000
267 #define MDIO_OP_BUSY 0x08000000
268 #define MDIO_AP_ENB 0x10000000
269 #define MDIO_MODE_EXT 0x40000000
270 #define MDIO_DATA_SHIFT 0
276 #define ALC_PHY_ADDR 0
278 #define ALC_PHY_STATUS 0x1418
279 #define PHY_STATUS_RECV_ENB 0x00000001
280 #define PHY_STATUS_GENERAL_MASK 0x0000FFFF
281 #define PHY_STATUS_OE_PWSP_MASK 0x07FF0000
282 #define PHY_STATUS_LPW_STATE 0x80000000
286 #define ALC_BIST0 0x141C
287 #define BIST0_ENB 0x00000001
288 #define BIST0_SRAM_FAIL 0x00000002
289 #define BIST0_FUSE_FLAG 0x00000004
292 #define ALC_BIST1 0x1420
293 #define BIST1_ENB 0x00000001
294 #define BIST1_SRAM_FAIL 0x00000002
295 #define BIST1_FUSE_FLAG 0x00000004
297 #define ALC_SERDES_LOCK 0x1424
298 #define SERDES_LOCK_DET 0x00000001
299 #define SERDES_LOCK_DET_ENB 0x00000002
300 #define SERDES_MAC_CLK_SLOWDOWN 0x00020000
301 #define SERDES_PHY_CLK_SLOWDOWN 0x00040000
303 #define ALC_LPI_CTL 0x1440
304 #define LPI_CTL_ENB 0x00000001
306 #define ALC_EXT_MDIO 0x1448
307 #define EXT_MDIO_REG_MASK 0x0000FFFF
308 #define EXT_MDIO_DEVADDR_MASK 0x001F0000
309 #define EXT_MDIO_REG_SHIFT 0
317 #define ALC_IDLE_DECISN_TIMER 0x1474
318 #define IDLE_DECISN_TIMER_DEFAULT_1MS 0x400
320 #define ALC_MAC_CFG 0x1480
321 #define MAC_CFG_TX_ENB 0x00000001
322 #define MAC_CFG_RX_ENB 0x00000002
323 #define MAC_CFG_TX_FC 0x00000004
324 #define MAC_CFG_RX_FC 0x00000008
325 #define MAC_CFG_LOOP 0x00000010
326 #define MAC_CFG_FULL_DUPLEX 0x00000020
327 #define MAC_CFG_TX_CRC_ENB 0x00000040
328 #define MAC_CFG_TX_AUTO_PAD 0x00000080
329 #define MAC_CFG_TX_LENCHK 0x00000100
330 #define MAC_CFG_RX_JUMBO_ENB 0x00000200
331 #define MAC_CFG_PREAMBLE_MASK 0x00003C00
332 #define MAC_CFG_VLAN_TAG_STRIP 0x00004000
333 #define MAC_CFG_PROMISC 0x00008000
334 #define MAC_CFG_TX_PAUSE 0x00010000
335 #define MAC_CFG_SCNT 0x00020000
336 #define MAC_CFG_SYNC_RST_TX 0x00040000
337 #define MAC_CFG_SIM_RST_TX 0x00080000
338 #define MAC_CFG_SPEED_MASK 0x00300000
339 #define MAC_CFG_SPEED_10_100 0x00100000
340 #define MAC_CFG_SPEED_1000 0x00200000
341 #define MAC_CFG_DBG_TX_BACKOFF 0x00400000
342 #define MAC_CFG_TX_JUMBO_ENB 0x00800000
343 #define MAC_CFG_RXCSUM_ENB 0x01000000
344 #define MAC_CFG_ALLMULTI 0x02000000
345 #define MAC_CFG_BCAST 0x04000000
346 #define MAC_CFG_DBG 0x08000000
347 #define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000
348 #define MAC_CFG_HASH_ALG_CRC32 0x20000000
349 #define MAC_CFG_SPEED_MODE_SW 0x40000000
350 #define MAC_CFG_FAST_PAUSE 0x80000000
354 #define ALC_IPG_IFG_CFG 0x1484
355 #define IPG_IFG_IPGT_MASK 0x0000007F
356 #define IPG_IFG_MIFG_MASK 0x0000FF00
357 #define IPG_IFG_IPG1_MASK 0x007F0000
358 #define IPG_IFG_IPG2_MASK 0x7F000000
359 #define IPG_IFG_IPGT_SHIFT 0
360 #define IPG_IFG_IPGT_DEFAULT 0x60
362 #define IPG_IFG_MIFG_DEFAULT 0x50
364 #define IPG_IFG_IPG1_DEFAULT 0x40
366 #define IPG_IFG_IPG2_DEFAULT 0x60
369 #define ALC_PAR0 0x1488
370 #define ALC_PAR1 0x148C
373 #define ALC_MAR0 0x1490
374 #define ALC_MAR1 0x1494
377 #define ALC_HDPX_CFG 0x1498
378 #define HDPX_CFG_LCOL_MASK 0x000003FF
379 #define HDPX_CFG_RETRY_MASK 0x0000F000
380 #define HDPX_CFG_EXC_DEF_EN 0x00010000
381 #define HDPX_CFG_NO_BACK_C 0x00020000
382 #define HDPX_CFG_NO_BACK_P 0x00040000
383 #define HDPX_CFG_ABEBE 0x00080000
384 #define HDPX_CFG_ABEBT_MASK 0x00F00000
385 #define HDPX_CFG_JAMIPG_MASK 0x0F000000
386 #define HDPX_CFG_LCOL_SHIFT 0
387 #define HDPX_CFG_LCOL_DEFAULT 0x37
389 #define HDPX_CFG_RETRY_DEFAULT 0x0F
391 #define HDPX_CFG_ABEBT_DEFAULT 0x0A
393 #define HDPX_CFG_JAMIPG_DEFAULT 0x07
395 #define ALC_FRAME_SIZE 0x149C
397 #define ALC_WOL_CFG 0x14A0
398 #define WOL_CFG_PATTERN 0x00000001
399 #define WOL_CFG_PATTERN_ENB 0x00000002
400 #define WOL_CFG_MAGIC 0x00000004
401 #define WOL_CFG_MAGIC_ENB 0x00000008
402 #define WOL_CFG_LINK_CHG 0x00000010
403 #define WOL_CFG_LINK_CHG_ENB 0x00000020
404 #define WOL_CFG_PATTERN_DET 0x00000100
405 #define WOL_CFG_MAGIC_DET 0x00000200
406 #define WOL_CFG_LINK_CHG_DET 0x00000400
407 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000
408 #define WOL_CFG_PATTERN0 0x00010000
409 #define WOL_CFG_PATTERN1 0x00020000
410 #define WOL_CFG_PATTERN2 0x00040000
411 #define WOL_CFG_PATTERN3 0x00080000
412 #define WOL_CFG_PATTERN4 0x00100000
413 #define WOL_CFG_PATTERN5 0x00200000
414 #define WOL_CFG_PATTERN6 0x00400000
417 #define ALC_PATTERN_CFG0 0x14A4
418 #define PATTERN_CFG_0_LEN_MASK 0x0000007F
419 #define PATTERN_CFG_1_LEN_MASK 0x00007F00
420 #define PATTERN_CFG_2_LEN_MASK 0x007F0000
421 #define PATTERN_CFG_3_LEN_MASK 0x7F000000
423 #define ALC_PATTERN_CFG1 0x14A8
424 #define PATTERN_CFG_4_LEN_MASK 0x0000007F
425 #define PATTERN_CFG_5_LEN_MASK 0x00007F00
426 #define PATTERN_CFG_6_LEN_MASK 0x007F0000
429 #define ALC_RSS_KEY0 0x14B0
431 #define ALC_RSS_KEY1 0x14B4
433 #define ALC_RSS_KEY2 0x14B8
435 #define ALC_RSS_KEY3 0x14BC
437 #define ALC_RSS_KEY4 0x14C0
439 #define ALC_RSS_KEY5 0x14C4
441 #define ALC_RSS_KEY6 0x14C8
443 #define ALC_RSS_KEY7 0x14CC
445 #define ALC_RSS_KEY8 0x14D0
447 #define ALC_RSS_KEY9 0x14D4
449 #define ALC_RSS_IDT_TABLE0 0x14E0
451 #define ALC_TD_PRI2_HEAD_ADDR_LO 0x14E0 /* AR816x */
453 #define ALC_RSS_IDT_TABLE1 0x14E4
455 #define ALC_TD_PRI3_HEAD_ADDR_LO 0x14E4 /* AR816x */
457 #define ALC_RSS_IDT_TABLE2 0x14E8
459 #define ALC_RSS_IDT_TABLE3 0x14EC
461 #define ALC_RSS_IDT_TABLE4 0x14F0
463 #define ALC_RSS_IDT_TABLE5 0x14F4
465 #define ALC_RSS_IDT_TABLE6 0x14F8
467 #define ALC_RSS_IDT_TABLE7 0x14FC
469 #define ALC_SRAM_RD0_ADDR 0x1500
471 #define ALC_SRAM_RD1_ADDR 0x1504
473 #define ALC_SRAM_RD2_ADDR 0x1508
475 #define ALC_SRAM_RD3_ADDR 0x150C
477 #define RD_HEAD_ADDR_MASK 0x000003FF
478 #define RD_TAIL_ADDR_MASK 0x03FF0000
479 #define RD_HEAD_ADDR_SHIFT 0
482 #define ALC_RD_NIC_LEN0 0x1510 /* 8 bytes unit */
483 #define RD_NIC_LEN_MASK 0x000003FF
485 #define ALC_RD_NIC_LEN1 0x1514
487 #define ALC_SRAM_TD_ADDR 0x1518
488 #define TD_HEAD_ADDR_MASK 0x000003FF
489 #define TD_TAIL_ADDR_MASK 0x03FF0000
490 #define TD_HEAD_ADDR_SHIFT 0
493 #define ALC_SRAM_TD_LEN 0x151C /* 8 bytes unit */
494 #define SRAM_TD_LEN_MASK 0x000003FF
496 #define ALC_SRAM_RX_FIFO_ADDR 0x1520
498 #define ALC_SRAM_RX_FIFO_LEN 0x1524
499 #define SRAM_RX_FIFO_LEN_MASK 0x00000FFF
500 #define SRAM_RX_FIFO_LEN_SHIFT 0
502 #define ALC_SRAM_TX_FIFO_ADDR 0x1528
504 #define ALC_SRAM_TX_FIFO_LEN 0x152C
506 #define ALC_SRAM_TCPH_ADDR 0x1530
507 #define SRAM_TCPH_ADDR_MASK 0x00000FFF
508 #define SRAM_PATH_ADDR_MASK 0x0FFF0000
509 #define SRAM_TCPH_ADDR_SHIFT 0
512 #define ALC_DMA_BLOCK 0x1534
513 #define DMA_BLOCK_LOAD 0x00000001
515 #define ALC_RX_BASE_ADDR_HI 0x1540
517 #define ALC_TX_BASE_ADDR_HI 0x1544
519 #define ALC_SMB_BASE_ADDR_HI 0x1548
521 #define ALC_SMB_BASE_ADDR_LO 0x154C
523 #define ALC_RD0_HEAD_ADDR_LO 0x1550
525 #define ALC_RD1_HEAD_ADDR_LO 0x1554
527 #define ALC_RD2_HEAD_ADDR_LO 0x1558
529 #define ALC_RD3_HEAD_ADDR_LO 0x155C
531 #define ALC_RD_RING_CNT 0x1560
532 #define RD_RING_CNT_MASK 0x00000FFF
533 #define RD_RING_CNT_SHIFT 0
535 #define ALC_RX_BUF_SIZE 0x1564
536 #define RX_BUF_SIZE_MASK 0x0000FFFF
543 #define ALC_RRD0_HEAD_ADDR_LO 0x1568
545 #define ALC_RRD1_HEAD_ADDR_LO 0x156C
547 #define ALC_RRD2_HEAD_ADDR_LO 0x1570
549 #define ALC_RRD3_HEAD_ADDR_LO 0x1574
551 #define ALC_RRD_RING_CNT 0x1578
552 #define RRD_RING_CNT_MASK 0x00000FFF
553 #define RRD_RING_CNT_SHIFT 0
555 #define ALC_TDH_HEAD_ADDR_LO 0x157C
557 #define ALC_TD_PRI1_HEAD_ADDR_LO 0x157C /* AR816x */
559 #define ALC_TDL_HEAD_ADDR_LO 0x1580
561 #define ALC_TD_PRI0_HEAD_ADDR_LO 0x1580 /* AR816x */
563 #define ALC_TD_RING_CNT 0x1584
564 #define TD_RING_CNT_MASK 0x0000FFFF
565 #define TD_RING_CNT_SHIFT 0
567 #define ALC_CMB_BASE_ADDR_LO 0x1588
569 #define ALC_TXQ_CFG 0x1590
570 #define TXQ_CFG_TD_BURST_MASK 0x0000000F
571 #define TXQ_CFG_IP_OPTION_ENB 0x00000010
572 #define TXQ_CFG_ENB 0x00000020
573 #define TXQ_CFG_ENHANCED_MODE 0x00000040
574 #define TXQ_CFG_8023_ENB 0x00000080
575 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000
576 #define TXQ_CFG_TD_BURST_SHIFT 0
580 #define ALC_TSO_OFFLOAD_THRESH 0x1594 /* 8 bytes unit */
581 #define TSO_OFFLOAD_THRESH_MASK 0x000007FF
582 #define TSO_OFFLOAD_ERRLGPKT_DROP_ENB 0x00000800
583 #define TSO_OFFLOAD_THRESH_SHIFT 0
587 #define ALC_TXF_WATER_MARK 0x1598 /* 8 bytes unit */
588 #define TXF_WATER_MARK_HI_MASK 0x00000FFF
589 #define TXF_WATER_MARK_LO_MASK 0x0FFF0000
590 #define TXF_WATER_MARK_BURST_ENB 0x80000000
591 #define TXF_WATER_MARK_LO_SHIFT 0
594 #define ALC_THROUGHPUT_MON 0x159C
595 #define THROUGHPUT_MON_RATE_MASK 0x00000003
596 #define THROUGHPUT_MON_ENB 0x00000080
597 #define THROUGHPUT_MON_RATE_SHIFT 0
599 #define ALC_RXQ_CFG 0x15A0
600 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK 0x00000003
601 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE 0x00000000
602 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M 0x00000001
603 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M 0x00000002
604 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M 0x00000003
605 #define RXQ_CFG_QUEUE1_ENB 0x00000010
606 #define RXQ_CFG_QUEUE2_ENB 0x00000020
607 #define RXQ_CFG_QUEUE3_ENB 0x00000040
608 #define RXQ_CFG_IPV6_CSUM_ENB 0x00000080
609 #define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00
610 #define RXQ_CFG_RSS_HASH_IPV4 0x00010000
611 #define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000
612 #define RXQ_CFG_RSS_HASH_IPV6 0x00040000
613 #define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000
614 #define RXQ_CFG_RD_BURST_MASK 0x03F00000
615 #define RXQ_CFG_RSS_MODE_DIS 0x00000000
616 #define RXQ_CFG_RSS_MODE_SQSINT 0x04000000
617 #define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000
618 #define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000
619 #define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000
620 #define RXQ_CFG_RSS_HASH_ENB 0x20000000
621 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000
622 #define RXQ_CFG_QUEUE0_ENB 0x80000000
631 #define RXQ_CFG_816X_RSS_HASH_IPV4 0x00000004
632 #define RXQ_CFG_816X_RSS_HASH_IPV4_TCP 0x00000008
633 #define RXQ_CFG_816X_RSS_HASH_IPV6 0x00000010
634 #define RXQ_CFG_816X_RSS_HASH_IPV6_TCP 0x00000020
635 #define RXQ_CFG_816X_RSS_HASH_MASK 0x0000003C
636 #define RXQ_CFG_816X_IPV6_PARSE_ENB 0x00000080
637 #define RXQ_CFG_816X_IDT_TBL_SIZE_MASK 0x0001FF00
639 #define RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT 0x100
641 #define ALC_RX_RD_FREE_THRESH 0x15A4 /* 8 bytes unit. */
642 #define RX_RD_FREE_THRESH_HI_MASK 0x0000003F
643 #define RX_RD_FREE_THRESH_LO_MASK 0x00000FC0
644 #define RX_RD_FREE_THRESH_HI_SHIFT 0
649 #define ALC_RX_FIFO_PAUSE_THRESH 0x15A8
650 #define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF
651 #define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000
652 #define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0
661 #define ALC_RD_DMA_CFG 0x15AC
662 #define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit */
663 #define RD_DMA_CFG_TIMER_MASK 0xFFFF0000
664 #define RD_DMA_CFG_THRESH_SHIFT 0
666 #define RD_DMA_CFG_THRESH_DEFAULT 0x100
667 #define RD_DMA_CFG_TIMER_DEFAULT 0
671 #define ALC_RSS_HASH_VALUE 0x15B0
673 #define ALC_RSS_HASH_FLAG 0x15B4
675 #define ALC_RSS_CPU 0x15B8
677 #define ALC_DMA_CFG 0x15C0
678 #define DMA_CFG_IN_ORDER 0x00000001
679 #define DMA_CFG_ENH_ORDER 0x00000002
680 #define DMA_CFG_OUT_ORDER 0x00000004
681 #define DMA_CFG_RCB_64 0x00000000
682 #define DMA_CFG_RCB_128 0x00000008
683 #define DMA_CFG_PEND_AUTO_RST 0x00000008
684 #define DMA_CFG_RD_BURST_128 0x00000000
685 #define DMA_CFG_RD_BURST_256 0x00000010
686 #define DMA_CFG_RD_BURST_512 0x00000020
687 #define DMA_CFG_RD_BURST_1024 0x00000030
688 #define DMA_CFG_RD_BURST_2048 0x00000040
689 #define DMA_CFG_RD_BURST_4096 0x00000050
690 #define DMA_CFG_WR_BURST_128 0x00000000
691 #define DMA_CFG_WR_BURST_256 0x00000080
692 #define DMA_CFG_WR_BURST_512 0x00000100
693 #define DMA_CFG_WR_BURST_1024 0x00000180
694 #define DMA_CFG_WR_BURST_2048 0x00000200
695 #define DMA_CFG_WR_BURST_4096 0x00000280
696 #define DMA_CFG_RD_REQ_PRI 0x00000400
697 #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800
698 #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000
699 #define DMA_CFG_CMB_ENB 0x00100000
700 #define DMA_CFG_SMB_ENB 0x00200000
701 #define DMA_CFG_CMB_NOW 0x00400000
702 #define DMA_CFG_SMB_DIS 0x01000000
703 #define DMA_CFG_RD_CHNL_SEL_MASK 0x0C000000
704 #define DMA_CFG_RD_CHNL_SEL_1 0x00000000
705 #define DMA_CFG_RD_CHNL_SEL_2 0x04000000
706 #define DMA_CFG_RD_CHNL_SEL_3 0x08000000
707 #define DMA_CFG_RD_CHNL_SEL_4 0x0C000000
708 #define DMA_CFG_WSRAM_RDCTL 0x10000000
709 #define DMA_CFG_RD_PEND_CLR 0x20000000
710 #define DMA_CFG_WR_PEND_CLR 0x40000000
711 #define DMA_CFG_SMB_NOW 0x80000000
712 #define DMA_CFG_RD_BURST_MASK 0x07
714 #define DMA_CFG_WR_BURST_MASK 0x07
721 #define ALC_SMB_STAT_TIMER 0x15C4
722 #define SMB_STAT_TIMER_MASK 0x00FFFFFF
723 #define SMB_STAT_TIMER_SHIFT 0
725 #define ALC_CMB_TD_THRESH 0x15C8
726 #define CMB_TD_THRESH_MASK 0x0000FFFF
727 #define CMB_TD_THRESH_SHIFT 0
729 #define ALC_CMB_TX_TIMER 0x15CC
730 #define CMB_TX_TIMER_MASK 0x0000FFFF
731 #define CMB_TX_TIMER_SHIFT 0
733 #define ALC_MSI_MAP_TBL1 0x15D0
735 #define ALC_MSI_ID_MAP 0x15D4
737 #define ALC_MSI_MAP_TBL2 0x15D8
739 #define ALC_MBOX_RD0_PROD_IDX 0x15E0
741 #define ALC_MBOX_RD1_PROD_IDX 0x15E4
743 #define ALC_MBOX_RD2_PROD_IDX 0x15E8
745 #define ALC_MBOX_RD3_PROD_IDX 0x15EC
747 #define ALC_MBOX_RD_PROD_MASK 0x0000FFFF
748 #define MBOX_RD_PROD_SHIFT 0
750 #define ALC_MBOX_TD_PROD_IDX 0x15F0
751 #define MBOX_TD_PROD_HI_IDX_MASK 0x0000FFFF
752 #define MBOX_TD_PROD_LO_IDX_MASK 0xFFFF0000
753 #define MBOX_TD_PROD_HI_IDX_SHIFT 0
756 #define ALC_MBOX_TD_PRI1_PROD_IDX 0x15F0 /* 16 bits AR816x */
758 #define ALC_MBOX_TD_PRI0_PROD_IDX 0x15F2 /* 16 bits AR816x */
760 #define ALC_MBOX_TD_CONS_IDX 0x15F4
761 #define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF
762 #define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000
763 #define MBOX_TD_CONS_HI_IDX_SHIFT 0
766 #define ALC_MBOX_TD_PRI1_CONS_IDX 0x15F4 /* 16 bits AR816x */
768 #define ALC_MBOX_TD_PRI0_CONS_IDX 0x15F6 /* 16 bits AR816x */
770 #define ALC_MBOX_RD01_CONS_IDX 0x15F8
771 #define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF
772 #define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000
773 #define MBOX_RD0_CONS_IDX_SHIFT 0
776 #define ALC_MBOX_RD23_CONS_IDX 0x15FC
777 #define MBOX_RD2_CONS_IDX_MASK 0x0000FFFF
778 #define MBOX_RD3_CONS_IDX_MASK 0xFFFF0000
779 #define MBOX_RD2_CONS_IDX_SHIFT 0
782 #define ALC_INTR_STATUS 0x1600
783 #define INTR_SMB 0x00000001
784 #define INTR_TIMER 0x00000002
785 #define INTR_MANUAL_TIMER 0x00000004
786 #define INTR_RX_FIFO_OFLOW 0x00000008
787 #define INTR_RD0_UNDERRUN 0x00000010
788 #define INTR_RD1_UNDERRUN 0x00000020
789 #define INTR_RD2_UNDERRUN 0x00000040
790 #define INTR_RD3_UNDERRUN 0x00000080
791 #define INTR_TX_FIFO_UNDERRUN 0x00000100
792 #define INTR_DMA_RD_TO_RST 0x00000200
793 #define INTR_DMA_WR_TO_RST 0x00000400
794 #define INTR_TX_CREDIT 0x00000800
795 #define INTR_GPHY 0x00001000
796 #define INTR_GPHY_LOW_PW 0x00002000
797 #define INTR_TXQ_TO_RST 0x00004000
798 #define INTR_TX_PKT0 0x00008000
799 #define INTR_RX_PKT0 0x00010000
800 #define INTR_RX_PKT1 0x00020000
801 #define INTR_RX_PKT2 0x00040000
802 #define INTR_RX_PKT3 0x00080000
803 #define INTR_MAC_RX 0x00100000
804 #define INTR_MAC_TX 0x00200000
805 #define INTR_UNDERRUN 0x00400000
806 #define INTR_FRAME_ERROR 0x00800000
807 #define INTR_FRAME_OK 0x01000000
808 #define INTR_CSUM_ERROR 0x02000000
809 #define INTR_PHY_LINK_DOWN 0x04000000
810 #define INTR_DIS_INT 0x80000000
813 #define INTR_TX_PKT1 0x00000020
814 #define INTR_TX_PKT2 0x00000040
815 #define INTR_TX_PKT3 0x00000080
816 #define INTR_RX_PKT4 0x08000000
817 #define INTR_RX_PKT5 0x10000000
818 #define INTR_RX_PKT6 0x20000000
819 #define INTR_RX_PKT7 0x40000000
822 #define ALC_INTR_MASK 0x1604
843 #define ALC_INTR_RETRIG_TIMER 0x1608
844 #define INTR_RETRIG_TIMER_MASK 0x0000FFFF
845 #define INTR_RETRIG_TIMER_SHIFT 0
847 #define ALC_HDS_CFG 0x160C
848 #define HDS_CFG_ENB 0x00000001
849 #define HDS_CFG_BACKFILLSIZE_MASK 0x000FFF00
850 #define HDS_CFG_MAX_HDRSIZE_MASK 0xFFF00000
854 #define ALC_MBOX_TD_PRI3_PROD_IDX 0x1618 /* 16 bits AR816x */
856 #define ALC_MBOX_TD_PRI2_PROD_IDX 0x161A /* 16 bits AR816x */
858 #define ALC_MBOX_TD_PRI3_CONS_IDX 0x161C /* 16 bits AR816x */
860 #define ALC_MBOX_TD_PRI2_CONS_IDX 0x161E /* 16 bits AR816x */
863 #define ALC_RX_MIB_BASE 0x1700
865 #define ALC_TX_MIB_BASE 0x1760
867 #define ALC_DRV 0x1804 /* AR816x */
868 #define DRV_ASPM_SPD10LMT_1M 0x00000000
869 #define DRV_ASPM_SPD10LMT_10M 0x00000001
870 #define DRV_ASPM_SPD10LMT_100M 0x00000002
871 #define DRV_ASPM_SPD10LMT_NO 0x00000003
872 #define DRV_ASPM_SPD10LMT_MASK 0x00000003
873 #define DRV_ASPM_SPD100LMT_1M 0x00000000
874 #define DRV_ASPM_SPD100LMT_10M 0x00000004
875 #define DRV_ASPM_SPD100LMT_100M 0x00000008
876 #define DRV_ASPM_SPD100LMT_NO 0x0000000C
877 #define DRV_ASPM_SPD100LMT_MASK 0x0000000C
878 #define DRV_ASPM_SPD1000LMT_100M 0x00000000
879 #define DRV_ASPM_SPD1000LMT_NO 0x00000010
880 #define DRV_ASPM_SPD1000LMT_1M 0x00000020
881 #define DRV_ASPM_SPD1000LMT_10M 0x00000030
882 #define DRV_ASPM_SPD1000LMT_MASK 0x00000000
883 #define DRV_WOLCAP_BIOS_EN 0x00000100
884 #define DRV_WOLMAGIC_EN 0x00000200
885 #define DRV_WOLLINKUP_EN 0x00000400
886 #define DRV_WOLPATTERN_EN 0x00000800
887 #define DRV_AZ_EN 0x00001000
888 #define DRV_WOLS5_BIOS_EN 0x00010000
889 #define DRV_WOLS5_EN 0x00020000
890 #define DRV_DISABLE 0x00040000
891 #define DRV_PHY_MASK 0x1FE00000
892 #define DRV_PHY_EEE 0x00200000
893 #define DRV_PHY_APAUSE 0x00400000
894 #define DRV_PHY_PAUSE 0x00800000
895 #define DRV_PHY_DUPLEX 0x01000000
896 #define DRV_PHY_10 0x02000000
897 #define DRV_PHY_100 0x04000000
898 #define DRV_PHY_1000 0x08000000
899 #define DRV_PHY_AUTO 0x10000000
902 #define ALC_CLK_GATING_CFG 0x1814
903 #define CLK_GATING_DMAW_ENB 0x0001
904 #define CLK_GATING_DMAR_ENB 0x0002
905 #define CLK_GATING_TXQ_ENB 0x0004
906 #define CLK_GATING_RXQ_ENB 0x0008
907 #define CLK_GATING_TXMAC_ENB 0x0010
908 #define CLK_GATING_RXMAC_ENB 0x0020
910 #define ALC_DEBUG_DATA0 0x1900
912 #define ALC_DEBUG_DATA1 0x1904
914 #define ALC_MSI_RETRANS_TIMER 0x1920
915 #define MSI_RETRANS_TIMER_MASK 0x0000FFFF
916 #define MSI_RETRANS_MASK_SEL_STD 0x00000000
917 #define MSI_RETRANS_MASK_SEL_LINE 0x00010000
918 #define MSI_RETRANS_TIMER_SHIFT 0
920 #define ALC_WRR 0x1938
921 #define WRR_PRI0_MASK 0x0000001F
922 #define WRR_PRI1_MASK 0x00001F00
923 #define WRR_PRI2_MASK 0x001F0000
924 #define WRR_PRI3_MASK 0x1F000000
925 #define WRR_PRI_RESTRICT_MASK 0x60000000
926 #define WRR_PRI_RESTRICT_ALL 0x00000000
927 #define WRR_PRI_RESTRICT_HI 0x20000000
928 #define WRR_PRI_RESTRICT_HI2 0x40000000
929 #define WRR_PRI_RESTRICT_NONE 0x60000000
930 #define WRR_PRI0_SHIFT 0
937 #define ALC_HQTD_CFG 0x193C
938 #define HQTD_CFG_Q1_BURST_MASK 0x0000000F
939 #define HQTD_CFG_Q2_BURST_MASK 0x000000F0
940 #define HQTD_CFG_Q3_BURST_MASK 0x00000F00
941 #define HQTD_CFG_BURST_ENB 0x80000000
942 #define HQTD_CFG_Q1_BURST_SHIFT 0
946 #define ALC_MISC 0x19C0
947 #define MISC_INTNLOSC_OPEN 0x00000008
948 #define MISC_ISO_ENB 0x00001000
949 #define MISC_PSW_OCP_MASK 0x00E00000
953 #define ALC_MISC2 0x19C8
954 #define MISC2_CALB_START 0x00000001
956 #define ALC_MISC3 0x19CC
957 #define MISC3_25M_NOTO_INTNL 0x00000001
958 #define MISC3_25M_BY_SW 0x00000002
960 #define ALC_MII_DBG_ADDR 0x1D
961 #define ALC_MII_DBG_DATA 0x1E
963 #define MII_ANA_CFG0 0x00
964 #define ANA_RESTART_CAL 0x0001
965 #define ANA_MANUL_SWICH_ON_MASK 0x001E
966 #define ANA_MAN_ENABLE 0x0020
967 #define ANA_SEL_HSP 0x0040
968 #define ANA_EN_HB 0x0080
969 #define ANA_EN_HBIAS 0x0100
970 #define ANA_OEN_125M 0x0200
971 #define ANA_EN_LCKDT 0x0400
972 #define ANA_LCKDT_PHY 0x0800
973 #define ANA_AFE_MODE 0x1000
974 #define ANA_VCO_SLOW 0x2000
975 #define ANA_VCO_FAST 0x4000
976 #define ANA_SEL_CLK125M_DSP 0x8000
979 #define MII_DBG_ANACTL 0x00
980 #define DBG_ANACTL_DEFAULT 0x02EF
982 #define MII_ANA_CFG4 0x04
983 #define ANA_IECHO_ADJ_MASK 0x0F
984 #define ANA_IECHO_ADJ_3_MASK 0x000F
985 #define ANA_IECHO_ADJ_2_MASK 0x00F0
986 #define ANA_IECHO_ADJ_1_MASK 0x0F00
987 #define ANA_IECHO_ADJ_0_MASK 0xF000
988 #define ANA_IECHO_ADJ_3_SHIFT 0
993 #define MII_DBG_SYSMODCTL 0x04
994 #define DBG_SYSMODCTL_DEFAULT 0xBB8B
996 #define MII_ANA_CFG5 0x05
997 #define ANA_SERDES_CDR_BW_MASK 0x0003
998 #define ANA_MS_PAD_DBG 0x0004
999 #define ANA_SPEEDUP_DBG 0x0008
1000 #define ANA_SERDES_TH_LOS_MASK 0x0030
1001 #define ANA_SERDES_EN_DEEM 0x0040
1002 #define ANA_SERDES_TXELECIDLE 0x0080
1003 #define ANA_SERDES_BEACON 0x0100
1004 #define ANA_SERDES_HALFTXDR 0x0200
1005 #define ANA_SERDES_SEL_HSP 0x0400
1006 #define ANA_SERDES_EN_PLL 0x0800
1007 #define ANA_SERDES_EN 0x1000
1008 #define ANA_SERDES_EN_LCKDT 0x2000
1009 #define ANA_SERDES_CDR_BW_SHIFT 0
1012 #define MII_DBG_SRDSYSMOD 0x05
1013 #define DBG_SRDSYSMOD_DEFAULT 0x2C46
1015 #define MII_ANA_CFG11 0x0B
1016 #define ANA_PS_HIB_EN 0x8000
1018 #define MII_DBG_HIBNEG 0x0B
1019 #define DBG_HIBNEG_HIB_PULSE 0x1000
1020 #define DBG_HIBNEG_PSHIB_EN 0x8000
1021 #define DBG_HIBNEG_DEFAULT 0xBC40
1023 #define MII_ANA_CFG18 0x12
1024 #define ANA_TEST_MODE_10BT_01MASK 0x0003
1025 #define ANA_LOOP_SEL_10BT 0x0004
1026 #define ANA_RGMII_MODE_SW 0x0008
1027 #define ANA_EN_LONGECABLE 0x0010
1028 #define ANA_TEST_MODE_10BT_2 0x0020
1029 #define ANA_EN_10BT_IDLE 0x0400
1030 #define ANA_EN_MASK_TB 0x0800
1031 #define ANA_TRIGGER_SEL_TIMER_MASK 0x3000
1032 #define ANA_INTERVAL_SEL_TIMER_MASK 0xC000
1033 #define ANA_TEST_MODE_10BT_01SHIFT 0
1037 #define MII_DBG_TST10BTCFG 0x12
1038 #define DBG_TST10BTCFG_DEFAULT 0x4C04
1040 #define MII_DBG_AZ_ANADECT 0x15
1041 #define DBG_AZ_ANADECT_DEFAULT 0x3220
1042 #define DBG_AZ_ANADECT_LONG 0x3210
1044 #define MII_DBG_MSE16DB 0x18
1045 #define DBG_MSE16DB_UP 0x05EA
1046 #define DBG_MSE16DB_DOWN 0x02EA
1048 #define MII_DBG_MSE20DB 0x1C
1049 #define DBG_MSE20DB_TH_MASK 0x01FC
1050 #define DBG_MSE20DB_TH_DEFAULT 0x2E
1051 #define DBG_MSE20DB_TH_HI 0x54
1054 #define MII_DBG_AGC 0x23
1055 #define DBG_AGC_2_VGA_MASK 0x3F00
1060 #define MII_ANA_CFG41 0x29
1061 #define ANA_TOP_PS_EN 0x8000
1063 #define MII_DBG_LEGCYPS 0x29
1064 #define DBG_LEGCYPS_ENB 0x8000
1065 #define DBG_LEGCYPS_DEFAULT 0x129D
1067 #define MII_ANA_CFG54 0x36
1068 #define ANA_LONG_CABLE_TH_100_MASK 0x003F
1069 #define ANA_DESERVED 0x0040
1070 #define ANA_EN_LIT_CH 0x0080
1071 #define ANA_SHORT_CABLE_TH_100_MASK 0x3F00
1072 #define ANA_BP_BAD_LINK_ACCUM 0x4000
1073 #define ANA_BP_SMALL_BW 0x8000
1074 #define ANA_LONG_CABLE_TH_100_SHIFT 0
1077 #define MII_DBG_TST100BTCFG 0x36
1078 #define DBG_TST100BTCFG_DEFAULT 0xE12C
1080 #define MII_DBG_GREENCFG 0x3B
1081 #define DBG_GREENCFG_DEFAULT 0x7078
1083 #define MII_DBG_GREENCFG2 0x3D
1084 #define DBG_GREENCFG2_GATE_DFSE_EN 0x0080
1085 #define DBG_GREENCFG2_BP_GREEN 0x8000
1090 #define MII_EXT_CLDCTL3 0x8003
1091 #define EXT_CLDCTL3_BP_CABLE1TH_DET_GT 0x8000
1093 #define MII_EXT_CLDCTL5 0x8005
1094 #define EXT_CLDCTL5_BP_VD_HLFBIAS 0x4000
1096 #define MII_EXT_CLDCTL6 0x8006
1097 #define EXT_CLDCTL6_CAB_LEN_MASK 0x00FF
1098 #define EXT_CLDCTL6_CAB_LEN_SHIFT 0
1102 #define MII_EXT_VDRVBIAS 0x8062
1108 #define MII_EXT_ANEG_LOCAL_EEEADV 0x3C
1109 #define ANEG_LOCA_EEEADV_100BT 0x0002
1110 #define ANEG_LOCA_EEEADV_1000BT 0x0004
1112 #define MII_EXT_ANEG_AFE 0x801A
1113 #define ANEG_AFEE_10BT_100M_TH 0x0040
1115 #define MII_EXT_ANEG_S3DIG10 0x8023
1116 #define ANEG_S3DIG10_SL 0x0001
1117 #define ANEG_S3DIG10_DEFAULT 0
1119 #define MII_EXT_ANEG_NLP78 0x8027
1120 #define ANEG_NLP78_120M_DEFAULT 0x8A05
1122 #define ALC_MT_MAGIC 0x1F00
1123 #define ALC_MT_MODE 0x1F04
1124 #define ALC_MT_SPEED 0x1F08
1125 #define ALC_MT_VERSION 0x1F0C
1127 #define MT_MAGIC 0xaabb1234
1128 #define MT_MODE_4Q BIT(0)
1199 #define RRD_CSUM_MASK 0x0000FFFF
1200 #define RRD_RD_CNT_MASK 0x000F0000
1201 #define RRD_RD_IDX_MASK 0xFFF00000
1202 #define RRD_CSUM_SHIFT 0
1213 #define RRD_VLAN_MASK 0x0000FFFF
1214 #define RRD_HEAD_LEN_MASK 0x00FF0000
1215 #define RRD_HDS_MASK 0x03000000
1216 #define RRD_HDS_NONE 0x00000000
1217 #define RRD_HDS_HEAD 0x01000000
1218 #define RRD_HDS_DATA 0x02000000
1219 #define RRD_CPU_MASK 0x0C000000
1220 #define RRD_HASH_FLAG_MASK 0xF0000000
1221 #define RRD_VLAN_SHIFT 0
1233 #define RRD_LEN_MASK 0x00003FFF
1234 #define RRD_LEN_SHIFT 0
1235 #define RRD_TCP_UDPCSUM_NOK 0x00004000
1236 #define RRD_IPCSUM_NOK 0x00008000
1237 #define RRD_VLAN_TAG 0x00010000
1238 #define RRD_PROTO_MASK 0x000E0000
1239 #define RRD_PROTO_IPV4 0x00020000
1240 #define RRD_PROTO_IPV6 0x000C0000
1241 #define RRD_ERR_SUM 0x00100000
1242 #define RRD_ERR_CRC 0x00200000
1243 #define RRD_ERR_ALIGN 0x00400000
1244 #define RRD_ERR_TRUNC 0x00800000
1245 #define RRD_ERR_RUNT 0x01000000
1246 #define RRD_ERR_ICMP 0x02000000
1247 #define RRD_BCAST 0x04000000
1248 #define RRD_MCAST 0x08000000
1249 #define RRD_SNAP_LLC 0x10000000
1250 #define RRD_ETHER 0x00000000
1251 #define RRD_FIFO_FULL 0x20000000
1252 #define RRD_ERR_LENGTH 0x40000000
1253 #define RRD_VALID 0x80000000
1263 #define TD_BUFLEN_MASK 0x00003FFF
1264 #define TD_VLAN_MASK 0xFFFF0000
1265 #define TD_BUFLEN_SHIFT 0
1270 #define TD_L4HDR_OFFSET_MASK 0x000000FF /* byte unit */
1271 #define TD_TCPHDR_OFFSET_MASK 0x000000FF /* byte unit */
1272 #define TD_PLOAD_OFFSET_MASK 0x000000FF /* 2 bytes unit */
1273 #define TD_CUSTOM_CSUM 0x00000100
1274 #define TD_IPCSUM 0x00000200
1275 #define TD_TCPCSUM 0x00000400
1276 #define TD_UDPCSUM 0x00000800
1277 #define TD_TSO 0x00001000
1278 #define TD_TSO_DESCV1 0x00000000
1279 #define TD_TSO_DESCV2 0x00002000
1280 #define TD_CON_VLAN_TAG 0x00004000
1281 #define TD_INS_VLAN_TAG 0x00008000
1282 #define TD_IPV4_DESCV2 0x00010000
1283 #define TD_LLC_SNAP 0x00020000
1284 #define TD_ETHERNET 0x00000000
1285 #define TD_CUSTOM_CSUM_OFFSET_MASK 0x03FC0000 /* 2 bytes unit */
1286 #define TD_CUSTOM_CSUM_EVEN_PAD 0x40000000
1287 #define TD_MSS_MASK 0x7FFC0000
1288 #define TD_EOP 0x80000000
1289 #define TD_L4HDR_OFFSET_SHIFT 0
1290 #define TD_TCPHDR_OFFSET_SHIFT 0
1291 #define TD_PLOAD_OFFSET_SHIFT 0