Lines Matching +full:ati +full:- +full:target
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org>
108 return ch->disablephy ? ATA_SC_DET_DISABLE : val;
116 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
118 if (ctlr->ccc) {
119 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI));
120 ATA_OUTL(ctlr->r_mem, AHCI_CCCC,
121 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) |
124 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) &
129 ctlr->ccc, ctlr->cccv);
133 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
134 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
146 if ((ATA_INL(ctlr->r_mem, AHCI_VS) >= 0x00010200) &&
147 (ATA_INL(ctlr->r_mem, AHCI_CAP2) & AHCI_CAP2_BOH) &&
148 ((v = ATA_INL(ctlr->r_mem, AHCI_BOHC)) & AHCI_BOHC_OOS) == 0) {
150 ATA_OUTL(ctlr->r_mem, AHCI_BOHC, v | AHCI_BOHC_OOS);
155 v = ATA_INL(ctlr->r_mem, AHCI_BOHC);
164 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
166 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR);
167 for (timeout = 1000; timeout > 0; timeout--) {
169 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
177 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
179 if (ctlr->quirks & AHCI_Q_RESTORE_CAP) {
182 * This is write to a read-only register to restore its state.
183 * On fully standard-compliant hardware this is not needed and
187 ATA_OUTL(ctlr->r_mem, AHCI_CAP, ctlr->caps);
201 ctlr->dev = dev;
202 ctlr->ccc = 0;
204 device_get_unit(dev), "ccc", &ctlr->ccc);
205 mtx_init(&ctlr->ch_mtx, "AHCI channels lock", NULL, MTX_DEF);
208 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
209 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
210 ctlr->sc_iomem.rm_type = RMAN_ARRAY;
211 ctlr->sc_iomem.rm_descr = "I/O memory addresses";
212 if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
216 if ((error = rman_manage_region(&ctlr->sc_iomem,
217 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
219 rman_fini(&ctlr->sc_iomem);
223 version = ATA_INL(ctlr->r_mem, AHCI_VS);
224 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
226 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2);
227 if (ctlr->caps & AHCI_CAP_EMS)
228 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL);
230 if (ctlr->quirks & AHCI_Q_FORCE_PI) {
237 int nports = (ctlr->caps & AHCI_CAP_NPMASK) + 1;
238 int nmask = (1 << nports) - 1;
240 ATA_OUTL(ctlr->r_mem, AHCI_PI, nmask);
245 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI);
248 if ((ctlr->quirks & AHCI_Q_ALTSIG) &&
249 (ctlr->caps & AHCI_CAP_SPM) == 0)
250 ctlr->quirks |= AHCI_Q_NOBSYRES;
252 if (ctlr->quirks & AHCI_Q_1CH) {
253 ctlr->caps &= ~AHCI_CAP_NPMASK;
254 ctlr->ichannels &= 0x01;
256 if (ctlr->quirks & AHCI_Q_2CH) {
257 ctlr->caps &= ~AHCI_CAP_NPMASK;
258 ctlr->caps |= 1;
259 ctlr->ichannels &= 0x03;
261 if (ctlr->quirks & AHCI_Q_4CH) {
262 ctlr->caps &= ~AHCI_CAP_NPMASK;
263 ctlr->caps |= 3;
264 ctlr->ichannels &= 0x0f;
266 ctlr->channels = MAX(flsl(ctlr->ichannels),
267 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
268 if (ctlr->quirks & AHCI_Q_NOPMP)
269 ctlr->caps &= ~AHCI_CAP_SPM;
270 if (ctlr->quirks & AHCI_Q_NONCQ)
271 ctlr->caps &= ~AHCI_CAP_SNCQ;
272 if ((ctlr->caps & AHCI_CAP_CCCS) == 0)
273 ctlr->ccc = 0;
274 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC);
276 /* Create controller-wide DMA tag. */
278 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR :
281 ctlr->dma_coherent ? BUS_DMA_COHERENT : 0, NULL, NULL,
282 &ctlr->dma_tag)) {
284 rman_fini(&ctlr->sc_iomem);
292 bus_dma_tag_destroy(ctlr->dma_tag);
294 rman_fini(&ctlr->sc_iomem);
299 for (u = ctlr->ichannels; u != 0; u >>= 1)
301 ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3));
303 "direct", &ctlr->direct);
305 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT;
310 (ctlr->caps & AHCI_CAP_NPMASK) + 1,
313 (ctlr->caps & AHCI_CAP_SPM) ?
315 (ctlr->caps & AHCI_CAP_FBSS) ?
317 if (ctlr->quirks != 0) {
318 device_printf(dev, "quirks=0x%b\n", ctlr->quirks,
323 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"",
324 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"",
325 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"",
326 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"",
327 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"",
328 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"",
329 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"",
330 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"",
334 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"",
335 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"",
336 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"",
337 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"",
338 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"",
339 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"",
340 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1,
341 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"",
342 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"",
343 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"",
344 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
348 (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"",
349 (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"",
350 (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"",
351 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"",
352 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"",
353 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":"");
356 for (unit = 0; unit < ctlr->channels; unit++) {
363 if ((ctlr->ichannels & (1 << unit)) == 0)
367 for (; unit < ctlr->channels + ctlr->remapped_devices; unit++) {
376 int em = (ctlr->caps & AHCI_CAP_EMS) != 0;
400 for (i = 0; i < ctlr->numirqs; i++) {
401 if (ctlr->irqs[i].r_irq) {
402 bus_teardown_intr(dev, ctlr->irqs[i].r_irq,
403 ctlr->irqs[i].handle);
405 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq);
408 bus_dma_tag_destroy(ctlr->dma_tag);
410 rman_fini(&ctlr->sc_iomem);
412 mtx_destroy(&ctlr->ch_mtx);
422 if (ctlr->r_mem)
423 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
424 if (ctlr->r_msix_table)
426 ctlr->r_msix_tab_rid, ctlr->r_msix_table);
427 if (ctlr->r_msix_pba)
429 ctlr->r_msix_pba_rid, ctlr->r_msix_pba);
431 ctlr->r_msix_pba = ctlr->r_mem = ctlr->r_msix_table = NULL;
441 if (ctlr->numirqs > 1 &&
442 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) {
444 ctlr->numirqs = 1;
448 if (ctlr->numirqs > AHCI_MAX_IRQS) {
450 ctlr->numirqs, AHCI_MAX_IRQS);
451 ctlr->numirqs = AHCI_MAX_IRQS;
455 for (i = 0; i < ctlr->numirqs; i++) {
456 ctlr->irqs[i].ctlr = ctlr;
457 ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0);
458 if (ctlr->channels == 1 && !ctlr->ccc && ctlr->msi)
459 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
460 else if (ctlr->numirqs == 1 || i >= ctlr->channels ||
461 (ctlr->ccc && i == ctlr->cccv))
462 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL;
463 else if (ctlr->channels > ctlr->numirqs &&
464 i == ctlr->numirqs - 1)
465 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER;
467 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
468 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
469 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
473 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL,
474 (ctlr->irqs[i].mode != AHCI_IRQ_MODE_ONE) ? ahci_intr :
475 ((ctlr->quirks & AHCI_Q_EDGEIS) ? ahci_intr_one_edge :
477 &ctlr->irqs[i], &ctlr->irqs[i].handle))) {
482 if (ctlr->numirqs > 1) {
483 bus_describe_intr(dev, ctlr->irqs[i].r_irq,
484 ctlr->irqs[i].handle,
485 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ?
499 struct ahci_controller *ctlr = irq->ctlr;
504 if (irq->mode == AHCI_IRQ_MODE_ALL) {
506 if (ctlr->ccc)
507 is = ctlr->ichannels;
509 is = ATA_INL(ctlr->r_mem, AHCI_IS);
511 unit = irq->r_irq_rid - 1;
512 is = ATA_INL(ctlr->r_mem, AHCI_IS);
516 if (ctlr->ccc)
517 ise = 1 << ctlr->cccv;
519 if (ctlr->quirks & AHCI_Q_EDGEIS)
522 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise);
523 for (; unit < ctlr->channels; unit++) {
525 (arg = ctlr->interrupt[unit].argument)) {
526 ctlr->interrupt[unit].function(arg);
529 for (; unit < ctlr->channels + ctlr->remapped_devices; unit++) {
530 if ((arg = ctlr->interrupt[unit].argument)) {
531 ctlr->interrupt[unit].function(arg);
536 if (!(ctlr->quirks & AHCI_Q_EDGEIS))
537 ATA_OUTL(ctlr->r_mem, AHCI_IS, is);
538 ATA_RBL(ctlr->r_mem, AHCI_IS);
548 struct ahci_controller *ctlr = irq->ctlr;
552 unit = irq->r_irq_rid - 1;
553 if ((arg = ctlr->interrupt[unit].argument))
554 ctlr->interrupt[unit].function(arg);
556 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
557 ATA_RBL(ctlr->r_mem, AHCI_IS);
564 struct ahci_controller *ctlr = irq->ctlr;
568 unit = irq->r_irq_rid - 1;
570 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
571 if ((arg = ctlr->interrupt[unit].argument))
572 ctlr->interrupt[unit].function(arg);
573 ATA_RBL(ctlr->r_mem, AHCI_IS);
590 unit -= ctlr->channels;
600 offset = ctlr->remap_offset + unit * ctlr->remap_size;
601 size = ctlr->remap_size;
605 } else if ((ctlr->caps & AHCI_CAP_EMS) == 0) {
611 offset = (ctlr->emloc & 0xffff0000) >> 14;
612 size = (ctlr->emloc & 0x0000ffff) << 2;
614 if (*rid == 2 && (ctlr->capsem &
621 st = rman_get_start(ctlr->r_mem);
622 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
623 st + offset + size - 1, size, RF_ACTIVE, child);
627 bsh = rman_get_bushandle(ctlr->r_mem);
628 bst = rman_get_bustag(ctlr->r_mem);
636 res = ctlr->irqs[0].r_irq;
670 ctlr->interrupt[unit].function = function;
671 ctlr->interrupt[unit].argument = argument;
682 ctlr->interrupt[unit].function = NULL;
683 ctlr->interrupt[unit].argument = NULL;
717 return (ctlr->dma_tag);
725 mtx_lock(&ctlr->ch_mtx);
726 ctlr->ch[ch->unit] = ch;
727 mtx_unlock(&ctlr->ch_mtx);
735 mtx_lock(&ctlr->ch_mtx);
736 mtx_lock(&ch->mtx);
737 ctlr->ch[ch->unit] = NULL;
738 mtx_unlock(&ch->mtx);
739 mtx_unlock(&ctlr->ch_mtx);
749 mtx_lock(&ctlr->ch_mtx);
750 ch = ctlr->ch[n];
752 mtx_lock(&ch->mtx);
753 mtx_unlock(&ctlr->ch_mtx);
761 mtx_unlock(&ch->mtx);
779 value = ch->disablephy;
781 if (error != 0 || req->newptr == NULL || (value != 0 && value != 1))
784 mtx_lock(&ch->mtx);
785 ch->disablephy = value;
787 ahci_ch_deinit(ch->dev);
789 ahci_ch_init(ch->dev);
792 mtx_unlock(&ch->mtx);
808 ch->dev = dev;
809 ch->unit = (intptr_t)device_get_ivars(dev);
810 ch->caps = ctlr->caps;
811 ch->caps2 = ctlr->caps2;
812 ch->start = ctlr->ch_start;
813 ch->quirks = ctlr->quirks;
814 ch->vendorid = ctlr->vendorid;
815 ch->deviceid = ctlr->deviceid;
816 ch->subvendorid = ctlr->subvendorid;
817 ch->subdeviceid = ctlr->subdeviceid;
818 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1;
819 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF);
820 ch->pm_level = 0;
822 device_get_unit(dev), "pm_level", &ch->pm_level);
823 STAILQ_INIT(&ch->doneq);
824 if (ch->pm_level > 3)
825 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
826 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0);
828 if ((ctlr->quirks & AHCI_Q_SATA1_UNIT0) && ch->unit == 0)
830 if (ch->quirks & AHCI_Q_SATA2)
835 ch->user[i].revision = sata_rev;
836 ch->user[i].mode = 0;
837 ch->user[i].bytecount = 8192;
838 ch->user[i].tags = ch->numslots;
839 ch->user[i].caps = 0;
840 ch->curr[i] = ch->user[i];
841 if (ch->pm_level) {
842 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ |
846 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA |
850 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
853 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD);
854 version = ATA_INL(ctlr->r_mem, AHCI_VS);
855 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS))
856 ch->chcaps |= AHCI_P_CMD_FBSCP;
857 if (ch->caps2 & AHCI_CAP2_SDS)
858 ch->chscaps = ATA_INL(ch->r_mem, AHCI_P_DEVSLP);
861 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"",
862 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"",
863 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"",
864 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"",
865 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"",
866 (ch->chscaps & AHCI_P_DEVSLP_DSP) ? " DSP":"");
870 mtx_lock(&ch->mtx);
873 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
879 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
880 ctlr->direct ? ahci_ch_intr_direct : ahci_ch_intr,
881 ch, &ch->ih))) {
887 devq = cam_simq_alloc(ch->numslots);
894 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch,
895 device_get_unit(dev), (struct mtx *)&ch->mtx,
896 (ch->quirks & AHCI_Q_NOCCS) ? 1 : min(2, ch->numslots),
897 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0,
899 if (ch->sim == NULL) {
905 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
910 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
916 if (ch->pm_level > 3) {
917 callout_reset(&ch->pm_timer,
918 (ch->pm_level == 4) ? hz / 1000 : hz / 8,
921 mtx_unlock(&ch->mtx);
931 xpt_bus_deregister(cam_sim_path(ch->sim));
933 cam_sim_free(ch->sim, /*free_devq*/TRUE);
935 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
937 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
938 mtx_unlock(&ch->mtx);
939 mtx_destroy(&ch->mtx);
949 mtx_lock(&ch->mtx);
950 xpt_async(AC_LOST_DEVICE, ch->path, NULL);
952 if (ch->resetting) {
953 ch->resetting = 0;
954 xpt_release_simq(ch->sim, TRUE);
956 xpt_free_path(ch->path);
957 xpt_bus_deregister(cam_sim_path(ch->sim));
958 cam_sim_free(ch->sim, /*free_devq*/TRUE);
959 mtx_unlock(&ch->mtx);
961 if (ch->pm_level > 3)
962 callout_drain(&ch->pm_timer);
963 callout_drain(&ch->reset_timer);
964 bus_teardown_intr(dev, ch->r_irq, ch->ih);
965 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
971 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
972 mtx_destroy(&ch->mtx);
983 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
985 work = ch->dma.work_bus + AHCI_CL_OFFSET;
986 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff);
987 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32);
988 work = ch->dma.rfis_bus;
989 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff);
990 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32);
992 ATA_OUTL(ch->r_mem, AHCI_P_CMD,
994 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) |
995 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 )));
1007 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
1011 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0);
1013 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0);
1015 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER);
1018 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
1027 mtx_lock(&ch->mtx);
1028 xpt_freeze_simq(ch->sim, 1);
1030 if (ch->resetting) {
1031 ch->resetting = 0;
1032 callout_stop(&ch->reset_timer);
1033 xpt_release_simq(ch->sim, TRUE);
1035 while (ch->oslots)
1036 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100);
1038 mtx_unlock(&ch->mtx);
1047 mtx_lock(&ch->mtx);
1050 xpt_release_simq(ch->sim, TRUE);
1051 mtx_unlock(&ch->mtx);
1087 0, NULL, NULL, &ch->dma.work_tag);
1090 error = bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work,
1091 BUS_DMA_ZERO, &ch->dma.work_map);
1094 error = bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work,
1097 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1100 ch->dma.work_bus = dcba.maddr;
1102 if (ch->chcaps & AHCI_P_CMD_FBSCP)
1109 0, NULL, NULL, &ch->dma.rfis_tag);
1112 error = bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0,
1113 &ch->dma.rfis_map);
1116 error = bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis,
1119 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1122 ch->dma.rfis_bus = dcba.maddr;
1128 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag);
1134 device_printf(dev, "WARNING - DMA initialization failed, error %d\n",
1144 if (!(dcba->error = error))
1145 dcba->maddr = segs[0].ds_addr;
1153 if (ch->dma.data_tag) {
1154 bus_dma_tag_destroy(ch->dma.data_tag);
1155 ch->dma.data_tag = NULL;
1157 if (ch->dma.rfis_bus) {
1158 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map);
1159 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1160 ch->dma.rfis_bus = 0;
1161 ch->dma.rfis = NULL;
1163 if (ch->dma.work_bus) {
1164 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map);
1165 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1166 ch->dma.work_bus = 0;
1167 ch->dma.work = NULL;
1169 if (ch->dma.work_tag) {
1170 bus_dma_tag_destroy(ch->dma.work_tag);
1171 ch->dma.work_tag = NULL;
1182 bzero(ch->slot, sizeof(ch->slot));
1183 for (i = 0; i < ch->numslots; i++) {
1184 struct ahci_slot *slot = &ch->slot[i];
1186 slot->ch = ch;
1187 slot->slot = i;
1188 slot->state = AHCI_SLOT_EMPTY;
1189 slot->ct_offset = AHCI_CT_OFFSET + AHCI_CT_SIZE * i;
1190 slot->ccb = NULL;
1191 callout_init_mtx(&slot->timeout, &ch->mtx, 0);
1193 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
1194 device_printf(ch->dev, "FAILURE - create data_map\n");
1205 for (i = 0; i < ch->numslots; i++) {
1206 struct ahci_slot *slot = &ch->slot[i];
1208 callout_drain(&slot->timeout);
1209 if (slot->dma.data_map) {
1210 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
1211 slot->dma.data_map = NULL;
1220 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) ||
1221 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) {
1222 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
1227 device_printf(ch->dev, "CONNECT requested\n");
1229 device_printf(ch->dev, "DISCONNECT requested\n");
1234 if (xpt_create_path(&ccb->ccb_h.path, NULL,
1235 cam_sim_path(ch->sim),
1253 if (ch->pm_level == 0)
1256 status = ATA_INL(ch->r_mem, AHCI_P_CMD);
1261 dev = ch->dev;
1270 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim),
1284 if (ch->caps & AHCI_CAP_SSNTF)
1285 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status);
1287 device_printf(ch->dev, "SNTF 0x%04x\n", status);
1292 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) {
1303 mtx_assert(&ch->mtx, MA_OWNED);
1304 if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 ||
1305 ch->batch == 0) {
1310 STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe);
1320 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1322 mtx_lock(&ch->mtx);
1324 mtx_unlock(&ch->mtx);
1336 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1338 mtx_lock(&ch->mtx);
1339 ch->batch = 1;
1341 ch->batch = 0;
1346 STAILQ_CONCAT(&tmp_doneq, &ch->doneq);
1347 mtx_unlock(&ch->mtx);
1360 if (ch->numrslots != 0)
1362 work = ATA_INL(ch->r_mem, AHCI_P_CMD);
1363 if (ch->pm_level == 4)
1367 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work);
1378 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus);
1380 if (ch->numtslots != 0)
1381 cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1384 if (ch->numrslots != ch->numtslots)
1385 cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI);
1388 (ch->pm_present || ch->curr[0].atapi != 0)) {
1389 if (ch->caps & AHCI_CAP_SSNTF)
1390 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF);
1391 else if (ch->fbs_enabled) {
1392 u_int8_t *fis = ch->dma.rfis + 0x58;
1402 u_int8_t *fis = ch->dma.rfis + 0x58;
1411 serr = ATA_INL(ch->r_mem, AHCI_P_SERR);
1413 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr);
1423 if (ch->quirks & AHCI_Q_NOCCS) {
1428 cstatus |= ch->rslots;
1431 ccs = powerof2(cstatus) ? ffs(cstatus) - 1 : -1;
1433 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) &
1437 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD),
1438 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs);
1439 port = -1;
1440 if (ch->fbs_enabled) {
1441 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS);
1447 if (ch->numrslotspd[i] == 0)
1449 if (port == -1)
1452 port = -2;
1458 err = ch->rslots & cstatus;
1462 port = -1;
1465 ok = ch->rslots & ~cstatus;
1466 for (i = 0; i < ch->numslots; i++) {
1468 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE);
1472 if (ch->frozen) {
1473 union ccb *fccb = ch->frozen;
1474 ch->frozen = NULL;
1475 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1476 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1477 xpt_freeze_devq(fccb->ccb_h.path, 1);
1478 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1482 for (i = 0; i < ch->numslots; i++) {
1487 ch->slot[i].ccb->ccb_h.target_id != port)
1490 if (port != -2) {
1492 if (ch->numtslotspd[
1493 ch->slot[i].ccb->ccb_h.target_id] == 0) {
1505 ch->fatalerr = 1;
1508 if (ch->numtslots == 0 && i != ccs && port != -2)
1514 ahci_end_transaction(&ch->slot[i], et);
1520 if (ch->rslots != 0 && !ch->recoverycmd)
1521 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC);
1532 int t = ccb->ccb_h.target_id;
1534 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1535 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1537 if (((~ch->oslots) & (0xffffffff >> (32 -
1538 ch->curr[t].tags))) == 0)
1541 if (ch->fbs_enabled) {
1543 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0)
1547 if (ch->numrslots != 0 && ch->numtslots == 0)
1549 /* Tagged command while tagged to other target is active. */
1550 if (ch->numtslots != 0 &&
1551 ch->taggedtarget != ccb->ccb_h.target_id)
1556 if (ch->fbs_enabled) {
1558 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0)
1562 if (ch->numrslots != 0 && ch->numtslots != 0)
1566 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1567 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) {
1569 if (ch->numrslots != 0)
1573 if (ch->aslots != 0)
1586 tags = ch->numslots;
1587 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1588 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA))
1589 tags = ch->curr[ccb->ccb_h.target_id].tags;
1590 if (ch->lastslot + 1 < tags)
1591 tag = ffs(~(ch->oslots >> (ch->lastslot + 1)));
1594 if (tag == 0 || tag + ch->lastslot >= tags)
1595 tag = ffs(~ch->oslots) - 1;
1597 tag += ch->lastslot;
1598 ch->lastslot = tag;
1600 slot = &ch->slot[tag];
1601 slot->ccb = ccb;
1603 if (ch->numrslots == 0 && ch->pm_level > 3)
1604 callout_stop(&ch->pm_timer);
1606 ch->oslots |= (1 << tag);
1607 ch->numrslots++;
1608 ch->numrslotspd[ccb->ccb_h.target_id]++;
1609 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1610 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1611 ch->numtslots++;
1612 ch->numtslotspd[ccb->ccb_h.target_id]++;
1613 ch->taggedtarget = ccb->ccb_h.target_id;
1615 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1616 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)))
1617 ch->aslots |= (1 << tag);
1618 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1619 slot->state = AHCI_SLOT_LOADING;
1620 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb,
1623 slot->dma.nsegs = 0;
1633 struct ahci_channel *ch = slot->ch;
1639 device_printf(ch->dev, "DMA load error\n");
1645 ctp = (struct ahci_cmd_tab *)(ch->dma.work + slot->ct_offset);
1647 prd = &ctp->prd_tab[0];
1650 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK);
1652 slot->dma.nsegs = nsegs;
1653 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1654 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
1663 struct ahci_channel *ch = slot->ch;
1666 union ccb *ccb = slot->ccb;
1667 int port = ccb->ccb_h.target_id & 0x0f;
1669 uint8_t *fis = ch->dma.rfis + 0x40;
1674 ctp = (struct ahci_cmd_tab *)(ch->dma.work + slot->ct_offset);
1676 if (!(fis_size = ahci_setup_fis(ch, ctp, ccb, slot->slot))) {
1677 device_printf(ch->dev, "Setting up SATA FIS failed\n");
1683 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1685 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) |
1686 (ccb->ccb_h.func_code == XPT_SCSI_IO ?
1690 clp->prd_length = htole16(slot->dma.nsegs);
1692 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1693 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) {
1694 if (ccb->ataio.cmd.control & ATA_A_RESET) {
1709 clp->bytecount = 0;
1710 clp->cmd_flags = htole16(cmd_flags);
1711 clp->cmd_table_phys = htole64(ch->dma.work_bus + slot->ct_offset);
1712 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1714 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1717 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1718 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1719 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot);
1722 if (ch->fbs_enabled) {
1723 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN |
1727 slot->state = AHCI_SLOT_RUNNING;
1728 ch->rslots |= (1 << slot->slot);
1729 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot));
1731 if (ccb->ccb_h.func_code == XPT_ATA_IO &&
1732 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) {
1733 int count, timeout = ccb->ccb_h.timeout * 100;
1738 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot)))
1740 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) &&
1743 device_printf(ch->dev,
1745 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD));
1750 /* Workaround for ATI SB600/SB700 chipsets. */
1751 if (ccb->ccb_h.target_id == 15 &&
1752 (ch->quirks & AHCI_Q_ATI_PMP_BUG) &&
1753 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) {
1764 if (ch->quirks & AHCI_Q_MRVL_SR_DEL)
1768 * Marvell HBAs with non-RAID firmware do not wait for
1774 if ((ch->quirks & AHCI_Q_NOBSYRES) == 0 &&
1775 (ch->quirks & AHCI_Q_ATI_PMP_BUG) == 0 &&
1778 bus_dmamap_sync(ch->dma.rfis_tag,
1779 ch->dma.rfis_map, BUS_DMASYNC_POSTREAD);
1781 bus_dmamap_sync(ch->dma.rfis_tag,
1782 ch->dma.rfis_map, BUS_DMASYNC_PREREAD);
1790 device_printf(ch->dev, "Poll timeout on slot %d port %d\n",
1791 slot->slot, port);
1792 device_printf(ch->dev, "is %08x cs %08x ss %08x "
1794 ATA_INL(ch->r_mem, AHCI_P_IS),
1795 ATA_INL(ch->r_mem, AHCI_P_CI),
1796 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1797 ATA_INL(ch->r_mem, AHCI_P_TFD),
1798 ATA_INL(ch->r_mem, AHCI_P_SERR),
1799 ATA_INL(ch->r_mem, AHCI_P_CMD));
1805 ch->eslots |= (1 << slot->slot);
1810 callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout / 2,
1821 mtx_assert(&ch->mtx, MA_OWNED);
1823 for (i = 0; i < ch->numslots; i++) {
1825 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1827 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT);
1837 mtx_assert(&ch->mtx, MA_OWNED);
1838 for (i = 0; i < ch->numslots; i++) {
1839 struct ahci_slot *slot = &ch->slot[i];
1842 if (slot->state < AHCI_SLOT_RUNNING)
1844 if ((ch->toslots & (1 << i)) == 0)
1846 callout_reset_sbt(&slot->timeout,
1847 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
1857 struct ahci_channel *ch = slot->ch;
1858 device_t dev = ch->dev;
1864 if (slot->state < AHCI_SLOT_RUNNING)
1868 if (slot->state < AHCI_SLOT_EXECUTING) {
1870 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1871 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
1873 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot ||
1874 ch->fbs_enabled || ch->wrongccs)
1875 slot->state = AHCI_SLOT_EXECUTING;
1876 else if ((ch->rslots & (1 << ccs)) == 0) {
1877 ch->wrongccs = 1;
1878 slot->state = AHCI_SLOT_EXECUTING;
1881 callout_reset_sbt(&slot->timeout,
1882 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
1888 slot->slot, slot->ccb->ccb_h.target_id & 0x0f);
1891 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI),
1892 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1893 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR),
1894 ATA_INL(ch->r_mem, AHCI_P_CMD));
1897 if (ch->frozen) {
1898 union ccb *fccb = ch->frozen;
1899 ch->frozen = NULL;
1900 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1901 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1902 xpt_freeze_devq(fccb->ccb_h.path, 1);
1903 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1907 if (!ch->fbs_enabled && !ch->wrongccs) {
1909 ch->fatalerr = 1;
1911 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT);
1913 for (i = 0; i < ch->numslots; i++) {
1915 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1917 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
1921 if (ch->toslots == 0)
1922 xpt_freeze_simq(ch->sim, 1);
1923 ch->toslots |= (1 << slot->slot);
1924 if ((ch->rslots & ~ch->toslots) == 0)
1928 ch->rslots & ~ch->toslots);
1936 struct ahci_channel *ch = slot->ch;
1937 union ccb *ccb = slot->ccb;
1942 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1945 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1950 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1951 struct ata_res *res = &ccb->ataio.res;
1954 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) {
1955 u_int8_t *fis = ch->dma.rfis + 0x40;
1957 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1959 if (ch->fbs_enabled) {
1960 fis += ccb->ccb_h.target_id * 256;
1961 res->status = fis[2];
1962 res->error = fis[3];
1964 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD);
1966 res->status = tfd;
1967 res->error = tfd >> 8;
1969 res->lba_low = fis[4];
1970 res->lba_mid = fis[5];
1971 res->lba_high = fis[6];
1972 res->device = fis[7];
1973 res->lba_low_exp = fis[8];
1974 res->lba_mid_exp = fis[9];
1975 res->lba_high_exp = fis[10];
1976 res->sector_count = fis[12];
1977 res->sector_count_exp = fis[13];
1983 if ((ch->quirks & AHCI_Q_ALTSIG) &&
1984 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
1985 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) {
1986 sig = ATA_INL(ch->r_mem, AHCI_P_SIG);
1987 res->lba_high = sig >> 24;
1988 res->lba_mid = sig >> 16;
1989 res->lba_low = sig >> 8;
1990 res->sector_count = sig;
1994 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 &&
1995 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
1996 (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
1997 ccb->ataio.resid =
1998 ccb->ataio.dxfer_len - le32toh(clp->bytecount);
2001 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2002 (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
2003 ccb->csio.resid =
2004 ccb->csio.dxfer_len - le32toh(clp->bytecount);
2007 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
2008 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
2009 (ccb->ccb_h.flags & CAM_DIR_IN) ?
2011 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map);
2014 ch->eslots |= (1 << slot->slot);
2016 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) &&
2017 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
2018 xpt_freeze_devq(ccb->ccb_h.path, 1);
2019 ccb->ccb_h.status |= CAM_DEV_QFRZN;
2022 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2025 ccb->ccb_h.status |= CAM_REQ_CMP;
2026 if (ccb->ccb_h.func_code == XPT_SCSI_IO)
2027 ccb->csio.scsi_status = SCSI_STATUS_OK;
2030 ch->fatalerr = 1;
2031 ccb->ccb_h.status |= CAM_REQ_INVALID;
2034 ccb->ccb_h.status |= CAM_REQUEUE_REQ;
2038 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2039 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
2040 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
2042 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
2046 ch->fatalerr = 1;
2047 if (!ch->recoverycmd) {
2048 xpt_freeze_simq(ch->sim, 1);
2049 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2050 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2052 ccb->ccb_h.status |= CAM_UNCOR_PARITY;
2055 if (!ch->recoverycmd) {
2056 xpt_freeze_simq(ch->sim, 1);
2057 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2058 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2060 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
2063 ch->fatalerr = 1;
2064 ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
2067 ch->oslots &= ~(1 << slot->slot);
2068 ch->rslots &= ~(1 << slot->slot);
2069 ch->aslots &= ~(1 << slot->slot);
2070 slot->state = AHCI_SLOT_EMPTY;
2071 slot->ccb = NULL;
2073 ch->numrslots--;
2074 ch->numrslotspd[ccb->ccb_h.target_id]--;
2075 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
2076 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
2077 ch->numtslots--;
2078 ch->numtslotspd[ccb->ccb_h.target_id]--;
2082 lastto = (ch->toslots == (1 << slot->slot));
2083 ch->toslots &= ~(1 << slot->slot);
2085 xpt_release_simq(ch->sim, TRUE);
2089 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
2090 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
2091 (ccb->ataio.cmd.control & ATA_A_RESET) &&
2093 ccb->ataio.cmd.control &= ~ATA_A_RESET;
2097 /* If it was our READ LOG command - process it. */
2098 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) {
2100 /* If it was our REQUEST SENSE command - process it. */
2101 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) {
2105 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR &&
2106 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) {
2107 ch->hold[slot->slot] = ccb;
2108 ch->numhslots++;
2112 if (ch->rslots == 0) {
2113 /* if there was fatal error - reset port. */
2114 if (ch->toslots != 0 || ch->fatalerr) {
2118 if (ch->eslots != 0) {
2124 if (!ch->recoverycmd && ch->numhslots)
2127 /* If all the rest of commands are in timeout - give them chance. */
2128 } else if ((ch->rslots & ~ch->toslots) == 0 &&
2132 if (ch->frozen && !ahci_check_collision(ch, ch->frozen)) {
2133 union ccb *fccb = ch->frozen;
2134 ch->frozen = NULL;
2136 xpt_release_simq(ch->sim, TRUE);
2139 if (ch->numrslots == 0 && ch->pm_level > 3 &&
2140 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
2141 callout_schedule(&ch->pm_timer,
2142 (ch->pm_level == 4) ? hz / 1000 : hz / 8);
2155 for (i = 0; i < ch->numslots; i++) {
2156 if (ch->hold[i])
2161 device_printf(ch->dev, "Unable to allocate recovery command\n");
2163 /* We can't do anything -- complete held commands. */
2164 for (i = 0; i < ch->numslots; i++) {
2165 if (ch->hold[i] == NULL)
2167 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2168 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL;
2169 ahci_done(ch, ch->hold[i]);
2170 ch->hold[i] = NULL;
2171 ch->numhslots--;
2176 xpt_setup_ccb(&ccb->ccb_h, ch->hold[i]->ccb_h.path,
2177 ch->hold[i]->ccb_h.pinfo.priority);
2178 if (ch->hold[i]->ccb_h.func_code == XPT_ATA_IO) {
2180 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG;
2181 ccb->ccb_h.func_code = XPT_ATA_IO;
2182 ccb->ccb_h.flags = CAM_DIR_IN;
2183 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2184 ataio = &ccb->ataio;
2185 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT);
2186 if (ataio->data_ptr == NULL) {
2188 device_printf(ch->dev,
2192 ataio->dxfer_len = 512;
2193 bzero(&ataio->cmd, sizeof(ataio->cmd));
2194 ataio->cmd.flags = CAM_ATAIO_48BIT;
2195 ataio->cmd.command = 0x2F; /* READ LOG EXT */
2196 ataio->cmd.sector_count = 1;
2197 ataio->cmd.sector_count_exp = 0;
2198 ataio->cmd.lba_low = 0x10;
2199 ataio->cmd.lba_mid = 0;
2200 ataio->cmd.lba_mid_exp = 0;
2203 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE;
2204 ccb->ccb_h.recovery_slot = i;
2205 ccb->ccb_h.func_code = XPT_SCSI_IO;
2206 ccb->ccb_h.flags = CAM_DIR_IN;
2207 ccb->ccb_h.status = 0;
2208 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2209 csio = &ccb->csio;
2210 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data;
2211 csio->dxfer_len = ch->hold[i]->csio.sense_len;
2212 csio->cdb_len = 6;
2213 bzero(&csio->cdb_io, sizeof(csio->cdb_io));
2214 csio->cdb_io.cdb_bytes[0] = 0x03;
2215 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len;
2218 ch->recoverycmd = 1;
2219 xpt_freeze_simq(ch->sim, 1);
2230 ch->recoverycmd = 0;
2232 data = ccb->ataio.data_ptr;
2233 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP &&
2235 for (i = 0; i < ch->numslots; i++) {
2236 if (!ch->hold[i])
2238 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2241 res = &ch->hold[i]->ataio.res;
2242 res->status = data[2];
2243 res->error = data[3];
2244 res->lba_low = data[4];
2245 res->lba_mid = data[5];
2246 res->lba_high = data[6];
2247 res->device = data[7];
2248 res->lba_low_exp = data[8];
2249 res->lba_mid_exp = data[9];
2250 res->lba_high_exp = data[10];
2251 res->sector_count = data[12];
2252 res->sector_count_exp = data[13];
2254 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2255 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
2257 ahci_done(ch, ch->hold[i]);
2258 ch->hold[i] = NULL;
2259 ch->numhslots--;
2262 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
2263 device_printf(ch->dev, "Error while READ LOG EXT\n");
2265 device_printf(ch->dev, "Non-queued command error in READ LOG EXT\n");
2267 for (i = 0; i < ch->numslots; i++) {
2268 if (!ch->hold[i])
2270 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2272 ahci_done(ch, ch->hold[i]);
2273 ch->hold[i] = NULL;
2274 ch->numhslots--;
2277 free(ccb->ataio.data_ptr, M_AHCI);
2279 xpt_release_simq(ch->sim, TRUE);
2287 ch->recoverycmd = 0;
2289 i = ccb->ccb_h.recovery_slot;
2290 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) {
2291 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID;
2293 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2294 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL;
2296 ahci_done(ch, ch->hold[i]);
2297 ch->hold[i] = NULL;
2298 ch->numhslots--;
2300 xpt_release_simq(ch->sim, TRUE);
2309 if (ch->start)
2310 ch->start(ch);
2313 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF);
2315 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF);
2316 /* Configure FIS-based switching if supported. */
2317 if (ch->chcaps & AHCI_P_CMD_FBSCP) {
2318 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0;
2319 ATA_OUTL(ch->r_mem, AHCI_P_FBS,
2320 ch->fbs_enabled ? AHCI_P_FBS_EN : 0);
2323 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2325 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST |
2326 (ch->pm_present ? AHCI_P_CMD_PMA : 0));
2336 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2337 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST);
2343 device_printf(ch->dev, "stopping AHCI engine failed\n");
2346 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR);
2347 ch->eslots = 0;
2357 if (ch->caps & AHCI_CAP_SCLO) {
2358 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2360 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd);
2365 device_printf(ch->dev, "executing CLO failed\n");
2368 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO);
2379 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2380 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE);
2386 device_printf(ch->dev, "stopping AHCI FR engine failed\n");
2389 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR);
2398 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2399 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE);
2408 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) &
2412 device_printf(ch->dev,
2423 device_printf(ch->dev, "AHCI reset: device ready after %dms\n",
2433 if (ch->resetting == 0)
2435 ch->resetting--;
2436 if (ahci_wait_ready(ch, ch->resetting == 0 ? -1 : 0,
2437 (310 - ch->resetting) * 100) == 0) {
2438 ch->resetting = 0;
2440 xpt_release_simq(ch->sim, TRUE);
2443 if (ch->resetting == 0) {
2446 xpt_release_simq(ch->sim, TRUE);
2449 callout_schedule(&ch->reset_timer, hz / 10);
2455 struct ahci_controller *ctlr = device_get_softc(device_get_parent(ch->dev));
2458 xpt_freeze_simq(ch->sim, 1);
2460 device_printf(ch->dev, "AHCI reset...\n");
2462 if (ch->resetting) {
2463 ch->resetting = 0;
2464 callout_stop(&ch->reset_timer);
2465 xpt_release_simq(ch->sim, TRUE);
2468 if (ch->frozen) {
2469 union ccb *fccb = ch->frozen;
2470 ch->frozen = NULL;
2471 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
2472 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
2473 xpt_freeze_devq(fccb->ccb_h.path, 1);
2474 fccb->ccb_h.status |= CAM_DEV_QFRZN;
2480 for (i = 0; i < ch->numslots; i++) {
2482 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
2485 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
2487 for (i = 0; i < ch->numslots; i++) {
2488 if (!ch->hold[i])
2490 ahci_done(ch, ch->hold[i]);
2491 ch->hold[i] = NULL;
2492 ch->numhslots--;
2494 if (ch->toslots != 0)
2495 xpt_release_simq(ch->sim, TRUE);
2496 ch->eslots = 0;
2497 ch->toslots = 0;
2498 ch->wrongccs = 0;
2499 ch->fatalerr = 0;
2501 xpt_async(AC_BUS_RESET, ch->path, NULL);
2503 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
2507 device_printf(ch->dev,
2509 ch->devices = 0;
2511 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2512 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2514 xpt_release_simq(ch->sim, TRUE);
2518 device_printf(ch->dev, "AHCI reset: device found\n");
2524 ch->resetting = 310;
2526 ch->devices = 1;
2528 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2529 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2532 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC |
2533 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) |
2534 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR)));
2535 if (ch->resetting)
2536 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, ch);
2539 xpt_release_simq(ch->sim, TRUE);
2546 u_int8_t *fis = &ctp->cfis[0];
2550 fis[1] = (ccb->ccb_h.target_id & 0x0f);
2551 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2554 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2555 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA)
2558 fis[5] = ccb->csio.dxfer_len;
2559 fis[6] = ccb->csio.dxfer_len >> 8;
2563 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
2564 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes,
2565 ctp->acmd, ccb->csio.cdb_len);
2566 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len);
2567 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) {
2569 fis[2] = ccb->ataio.cmd.command;
2570 fis[3] = ccb->ataio.cmd.features;
2571 fis[4] = ccb->ataio.cmd.lba_low;
2572 fis[5] = ccb->ataio.cmd.lba_mid;
2573 fis[6] = ccb->ataio.cmd.lba_high;
2574 fis[7] = ccb->ataio.cmd.device;
2575 fis[8] = ccb->ataio.cmd.lba_low_exp;
2576 fis[9] = ccb->ataio.cmd.lba_mid_exp;
2577 fis[10] = ccb->ataio.cmd.lba_high_exp;
2578 fis[11] = ccb->ataio.cmd.features_exp;
2579 fis[12] = ccb->ataio.cmd.sector_count;
2580 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
2584 fis[13] = ccb->ataio.cmd.sector_count_exp;
2585 if (ccb->ataio.ata_flags & ATA_FLAG_ICC)
2586 fis[14] = ccb->ataio.icc;
2588 if (ccb->ataio.ata_flags & ATA_FLAG_AUX) {
2589 fis[16] = ccb->ataio.aux & 0xff;
2590 fis[17] = (ccb->ataio.aux >> 8) & 0xff;
2591 fis[18] = (ccb->ataio.aux >> 16) & 0xff;
2592 fis[19] = (ccb->ataio.aux >> 24) & 0xff;
2595 fis[15] = ccb->ataio.cmd.control;
2610 timeoutslot = ((ch->quirks & AHCI_Q_SLOWDEV) ? 5000 : 1000);
2612 status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
2621 device_printf(ch->dev, "SATA offline status=%08x\n",
2632 device_printf(ch->dev,
2639 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n",
2643 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff);
2653 if (ch->listening) {
2654 val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2656 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2657 ch->listening = 0;
2659 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision;
2669 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2674 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2675 detval | val | ((ch->pm_level > 0) ? 0 :
2678 if (ch->caps & AHCI_CAP_SSS) {
2679 val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2681 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2682 ch->listening = 1;
2683 } else if (ch->pm_level > 0)
2684 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
2694 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) {
2695 ccb->ccb_h.status = CAM_TID_INVALID;
2697 return (-1);
2699 if (ccb->ccb_h.target_lun != 0) {
2700 ccb->ccb_h.status = CAM_LUN_INVALID;
2702 return (-1);
2712 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n",
2713 ccb->ccb_h.func_code));
2716 switch (ccb->ccb_h.func_code) {
2722 if (ch->devices == 0 ||
2723 (ch->pm_present == 0 &&
2724 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) {
2725 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2728 ccb->ccb_h.recovery_type = RECOVERY_NONE;
2732 ch->frozen = ccb;
2734 xpt_freeze_simq(ch->sim, 1);
2741 ccb->ccb_h.status = CAM_REQ_INVALID;
2745 struct ccb_trans_settings *cts = &ccb->cts;
2750 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2751 d = &ch->curr[ccb->ccb_h.target_id];
2753 d = &ch->user[ccb->ccb_h.target_id];
2754 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION)
2755 d->revision = cts->xport_specific.sata.revision;
2756 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE)
2757 d->mode = cts->xport_specific.sata.mode;
2758 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT)
2759 d->bytecount = min(8192, cts->xport_specific.sata.bytecount);
2760 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS)
2761 d->tags = min(ch->numslots, cts->xport_specific.sata.tags);
2762 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM)
2763 ch->pm_present = cts->xport_specific.sata.pm_present;
2764 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI)
2765 d->atapi = cts->xport_specific.sata.atapi;
2766 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
2767 d->caps = cts->xport_specific.sata.caps;
2768 ccb->ccb_h.status = CAM_REQ_CMP;
2772 /* Get default/user set transfer settings for the target */
2774 struct ccb_trans_settings *cts = &ccb->cts;
2780 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2781 d = &ch->curr[ccb->ccb_h.target_id];
2783 d = &ch->user[ccb->ccb_h.target_id];
2784 cts->protocol = PROTO_UNSPECIFIED;
2785 cts->protocol_version = PROTO_VERSION_UNSPECIFIED;
2786 cts->transport = XPORT_SATA;
2787 cts->transport_version = XPORT_VERSION_UNSPECIFIED;
2788 cts->proto_specific.valid = 0;
2789 cts->xport_specific.sata.valid = 0;
2790 if (cts->type == CTS_TYPE_CURRENT_SETTINGS &&
2791 (ccb->ccb_h.target_id == 15 ||
2792 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) {
2793 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK;
2795 cts->xport_specific.sata.revision =
2797 cts->xport_specific.sata.valid |=
2800 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D;
2801 if (ch->pm_level) {
2802 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC))
2803 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ;
2804 if (ch->caps2 & AHCI_CAP2_APST)
2805 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST;
2807 if ((ch->caps & AHCI_CAP_SNCQ) &&
2808 (ch->quirks & AHCI_Q_NOAA) == 0)
2809 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA;
2810 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN;
2811 cts->xport_specific.sata.caps &=
2812 ch->user[ccb->ccb_h.target_id].caps;
2813 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2815 cts->xport_specific.sata.revision = d->revision;
2816 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
2817 cts->xport_specific.sata.caps = d->caps;
2818 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2820 cts->xport_specific.sata.mode = d->mode;
2821 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
2822 cts->xport_specific.sata.bytecount = d->bytecount;
2823 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT;
2824 cts->xport_specific.sata.pm_present = ch->pm_present;
2825 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM;
2826 cts->xport_specific.sata.tags = d->tags;
2827 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS;
2828 cts->xport_specific.sata.atapi = d->atapi;
2829 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI;
2830 ccb->ccb_h.status = CAM_REQ_CMP;
2836 ccb->ccb_h.status = CAM_REQ_CMP;
2840 ccb->ccb_h.status = CAM_REQ_INVALID;
2844 struct ccb_pathinq *cpi = &ccb->cpi;
2846 cpi->version_num = 1; /* XXX??? */
2847 cpi->hba_inquiry = PI_SDTR_ABLE;
2848 if (ch->caps & AHCI_CAP_SNCQ)
2849 cpi->hba_inquiry |= PI_TAG_ABLE;
2850 if (ch->caps & AHCI_CAP_SPM)
2851 cpi->hba_inquiry |= PI_SATAPM;
2852 cpi->target_sprt = 0;
2853 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED;
2854 if ((ch->quirks & AHCI_Q_NOAUX) == 0)
2855 cpi->hba_misc |= PIM_ATA_EXT;
2856 cpi->hba_eng_cnt = 0;
2857 if (ch->caps & AHCI_CAP_SPM)
2858 cpi->max_target = 15;
2860 cpi->max_target = 0;
2861 cpi->max_lun = 0;
2862 cpi->initiator_id = 0;
2863 cpi->bus_id = cam_sim_bus(sim);
2864 cpi->base_transfer_speed = 150000;
2865 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2866 strlcpy(cpi->hba_vid, "AHCI", HBA_IDLEN);
2867 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2868 cpi->unit_number = cam_sim_unit(sim);
2869 cpi->transport = XPORT_SATA;
2870 cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
2871 cpi->protocol = PROTO_ATA;
2872 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
2873 cpi->maxio = ctob(AHCI_SG_ENTRIES - 1);
2874 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */
2875 if (ch->quirks & AHCI_Q_MAXIO_64K)
2876 cpi->maxio = min(cpi->maxio, 128 * 512);
2877 cpi->hba_vendor = ch->vendorid;
2878 cpi->hba_device = ch->deviceid;
2879 cpi->hba_subvendor = ch->subvendorid;
2880 cpi->hba_subdevice = ch->subdeviceid;
2881 cpi->ccb_h.status = CAM_REQ_CMP;
2885 ccb->ccb_h.status = CAM_REQ_INVALID;
2898 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
2901 if (ch->resetting != 0 &&
2902 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) {
2903 ch->resetpolldiv = 1000;