Lines Matching +full:use +full:- +full:ring +full:- +full:sense
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
7 * Redistribution and use in source and binary forms, with or without
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
51 #define AE_ISR_RXS_OVERFLOW 0x00000020 /* Internal RxS ring overflow. */
84 #define AE_EADDR0_REG 0x1488 /* 5 - 2 bytes */
85 #define AE_EADDR1_REG 0x148c /* 1 - 0 bytes */
89 * L2 supports 64-bit addressing but all rings base addresses
92 #define AE_DESC_ADDR_HI_REG 0x1540 /* High 32 bits of ring base address. */
93 #define AE_RXD_ADDR_LO_REG 0x1554 /* Low 32 bits of RxD ring address. */
94 #define AE_TXD_ADDR_LO_REG 0x1544 /* Low 32 bits of TxD ring address. */
95 #define AE_TXS_ADDR_LO_REG 0x154c /* Low 32 bits of TxS ring address. */
96 #define AE_RXD_COUNT_REG 0x1558 /* Number of RxD descriptors in ring.
97 Should be 120-byte aligned (i.e.
99 have 128-byte alignment). */
100 #define AE_TXD_BUFSIZE_REG 0x1548 /* Size of TxD ring in 4-byte units.
101 Should be 4-byte aligned. */
102 #define AE_TXS_COUNT_REG 0x1550 /* Number of TxS descriptors in ring.
107 /* Padding to align frames on a 128-byte boundary. */
119 * Inter-frame gap configuration register.
123 #define AE_IFG_TXIPG_DEFAULT 0x60 /* 96-bit IFG time. */
127 #define AE_IFG_RXIPG_DEFAULT 0x50 /* 80-bit IFG time. */
131 #define AE_IFG_IPGR1_DEFAULT 0x40 /* Carrier-sense window. */
140 * Half-duplex mode configuration register.
154 /* Alternative binary exponential back-off time. */
159 /* IFG to start JAM for collision based flow control (8-bit time units).*/
166 /* No back-off on collision, immediately start the retransmission. */
168 /* No back-off on backpressure, immediately start the transmission. */
170 /* Alternative binary exponential back-off enable. */
194 * Cut-through configuration register.
196 #define AE_CUT_THRESH_REG 0x1590 /* Cut-through threshold in unknown units. */
200 * Flow-control configuration registers.
231 #define AE_MAC_FULL_DUPLEX 0x00000020 /* Enable full-duplex. */
244 PHY, if 0 - system clock. */
245 #define AE_HALFBUF_MASK 0xf0000000 /* Half-duplex retry buffer. */
278 * If bit is set then the corresponding module is in non-idle state.
343 * PHY-specific registers constants.