Lines Matching +full:dma +full:- +full:window

1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
55 #define	AE_ISR_DMAR_TIMEOUT	0x00000200	/* DMA read timeout. */
56 #define	AE_ISR_DMAW_TIMEOUT	0x00000400	/* DMA write timeout. */
84 #define	AE_EADDR0_REG		0x1488	/* 5 - 2 bytes */
85 #define	AE_EADDR1_REG		0x148c	/* 1 - 0 bytes */
89  * L2 supports 64-bit addressing but all rings base addresses
97 					   Should be 120-byte aligned (i.e.
99 					   have 128-byte alignment). */
100 #define	AE_TXD_BUFSIZE_REG	0x1548	/* Size of TxD ring in 4-byte units.
101 					   Should be 4-byte aligned. */
107 /* Padding to align frames on a 128-byte boundary. */
119  * Inter-frame gap configuration register.
123 #define	AE_IFG_TXIPG_DEFAULT	0x60	/* 96-bit IFG time. */
127 #define	AE_IFG_RXIPG_DEFAULT	0x50	/* 80-bit IFG time. */
131 #define	AE_IFG_IPGR1_DEFAULT	0x40	/* Carrier-sense window. */
135 #define	AE_IFG_IPGR2_DEFAULT	0x60	/* IFG window. */
140  * Half-duplex mode configuration register.
144 /* Collision window. */
154 /* Alternative binary exponential back-off time. */
159 /* IFG to start JAM for collision based flow control (8-bit time units).*/
166 /* No back-off on collision, immediately start the retransmission. */
168 /* No back-off on backpressure, immediately start the transmission. */
170 /* Alternative binary exponential back-off enable. */
194  * Cut-through configuration register.
196 #define	AE_CUT_THRESH_REG	0x1590	/* Cut-through threshold in unknown units. */
200  * Flow-control configuration registers.
214  * DMA configuration registers.
216 #define	AE_DMAREAD_REG		0x1580	/* Read DMA configuration register. */
218 #define	AE_DMAWRITE_REG		0x15a0	/* Write DMA configuration register. */
231 #define	AE_MAC_FULL_DUPLEX	0x00000020	/* Enable full-duplex. */
244 						   PHY, if 0 - system clock. */
245 #define	AE_HALFBUF_MASK		0xf0000000	/* Half-duplex retry buffer. */
278  * If bit is set then the corresponding module is in non-idle state.
343  * PHY-specific registers constants.