Lines Matching +full:irqs +full:- +full:map +full:- +full:range
1 /*-
2 * Copyright (c) 2005 Poul-Henning Kamp
142 sc = tc->tc_priv; in hpet_get_timecount()
143 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); in hpet_get_timecount()
151 sc = tc->tc_priv; in hpet_vdso_timehands()
152 vdso_th->th_algo = VDSO_TH_ALGO_X86_HPET; in hpet_vdso_timehands()
153 vdso_th->th_x86_shift = 0; in hpet_vdso_timehands()
154 vdso_th->th_x86_hpet_idx = device_get_unit(sc->dev); in hpet_vdso_timehands()
155 vdso_th->th_x86_pvc_last_systime = 0; in hpet_vdso_timehands()
156 vdso_th->th_x86_pvc_stable_mask = 0; in hpet_vdso_timehands()
157 bzero(vdso_th->th_res, sizeof(vdso_th->th_res)); in hpet_vdso_timehands()
158 return (sc->mmap_allow != 0); in hpet_vdso_timehands()
168 sc = tc->tc_priv; in hpet_vdso_timehands32()
169 vdso_th32->th_algo = VDSO_TH_ALGO_X86_HPET; in hpet_vdso_timehands32()
170 vdso_th32->th_x86_shift = 0; in hpet_vdso_timehands32()
171 vdso_th32->th_x86_hpet_idx = device_get_unit(sc->dev); in hpet_vdso_timehands32()
172 vdso_th32->th_x86_pvc_last_systime[0] = 0; in hpet_vdso_timehands32()
173 vdso_th32->th_x86_pvc_last_systime[1] = 0; in hpet_vdso_timehands32()
174 vdso_th32->th_x86_pvc_stable_mask = 0; in hpet_vdso_timehands32()
175 bzero(vdso_th32->th_res, sizeof(vdso_th32->th_res)); in hpet_vdso_timehands32()
176 return (sc->mmap_allow != 0); in hpet_vdso_timehands32()
185 val = bus_read_4(sc->mem_res, HPET_CONFIG); in hpet_enable()
186 if (sc->legacy_route) in hpet_enable()
191 bus_write_4(sc->mem_res, HPET_CONFIG, val); in hpet_enable()
199 val = bus_read_4(sc->mem_res, HPET_CONFIG); in hpet_disable()
201 bus_write_4(sc->mem_res, HPET_CONFIG, val); in hpet_disable()
207 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; in hpet_start()
209 struct hpet_softc *sc = mt->sc; in hpet_start()
212 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; in hpet_start()
214 t->mode = TIMER_PERIODIC; in hpet_start()
215 t->div = (sc->freq * period) >> 32; in hpet_start()
217 t->mode = TIMER_ONESHOT; in hpet_start()
218 t->div = 0; in hpet_start()
221 fdiv = (sc->freq * first) >> 32; in hpet_start()
223 fdiv = t->div; in hpet_start()
224 if (t->irq < 0) in hpet_start()
225 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); in hpet_start()
226 t->caps |= HPET_TCNF_INT_ENB; in hpet_start()
227 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); in hpet_start()
229 t->next = now + fdiv; in hpet_start()
230 if (t->mode == TIMER_PERIODIC && (t->caps & HPET_TCAP_PER_INT)) { in hpet_start()
231 t->caps |= HPET_TCNF_TYPE; in hpet_start()
232 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), in hpet_start()
233 t->caps | HPET_TCNF_VAL_SET); in hpet_start()
234 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), in hpet_start()
235 t->next); in hpet_start()
236 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), in hpet_start()
237 t->div); in hpet_start()
239 t->caps &= ~HPET_TCNF_TYPE; in hpet_start()
240 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), in hpet_start()
241 t->caps); in hpet_start()
242 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), in hpet_start()
243 t->next); in hpet_start()
245 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); in hpet_start()
246 if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) { in hpet_start()
256 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; in hpet_stop()
258 struct hpet_softc *sc = mt->sc; in hpet_stop()
260 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; in hpet_stop()
261 t->mode = TIMER_STOPPED; in hpet_stop()
262 t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); in hpet_stop()
263 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); in hpet_stop()
272 struct hpet_softc *sc = t->sc; in hpet_intr_single()
275 if (t->mode == TIMER_STOPPED) in hpet_intr_single()
277 /* Check that per-CPU timer interrupt reached right CPU. */ in hpet_intr_single()
278 if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) { in hpet_intr_single()
279 if ((++t->pcpu_misrouted) % 32 == 0) { in hpet_intr_single()
281 " (timer %d CPU %d -> %d)!\n", in hpet_intr_single()
282 t->num, t->pcpu_cpu, curcpu); in hpet_intr_single()
289 if ((t->mode == TIMER_PERIODIC && in hpet_intr_single()
290 (t->caps & HPET_TCAP_PER_INT) == 0) || in hpet_intr_single()
291 t->mode == TIMER_ONESHOT) { in hpet_intr_single()
292 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) + in hpet_intr_single()
293 sc->freq / 8; in hpet_intr_single()
294 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), in hpet_intr_single()
295 t->next); in hpet_intr_single()
299 if (t->mode == TIMER_PERIODIC && in hpet_intr_single()
300 (t->caps & HPET_TCAP_PER_INT) == 0) { in hpet_intr_single()
301 t->next += t->div; in hpet_intr_single()
302 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); in hpet_intr_single()
303 if ((int32_t)((now + t->div / 2) - t->next) > 0) in hpet_intr_single()
304 t->next = now + t->div / 2; in hpet_intr_single()
305 bus_write_4(sc->mem_res, in hpet_intr_single()
306 HPET_TIMER_COMPARATOR(t->num), t->next); in hpet_intr_single()
307 } else if (t->mode == TIMER_ONESHOT) in hpet_intr_single()
308 t->mode = TIMER_STOPPED; in hpet_intr_single()
309 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; in hpet_intr_single()
310 if (mt->et.et_active) in hpet_intr_single()
311 mt->et.et_event_cb(&mt->et, mt->et.et_arg); in hpet_intr_single()
322 val = bus_read_4(sc->mem_res, HPET_ISR); in hpet_intr()
324 bus_write_4(sc->mem_res, HPET_ISR, val); in hpet_intr()
325 val &= sc->useirq; in hpet_intr()
326 for (i = 0; i < sc->num_timers; i++) { in hpet_intr()
329 hpet_intr_single(&sc->t[i]); in hpet_intr()
342 return (sc->acpi_uid); in hpet_get_uid()
366 * Find an existing IRQ resource that matches the requested IRQ range
387 sc = cdev->si_drv1; in hpet_open()
388 if (!sc->mmap_allow) in hpet_open()
400 sc = cdev->si_drv1; in hpet_mmap()
401 if (offset >= rman_get_size(sc->mem_res)) in hpet_mmap()
403 if (!sc->mmap_allow_write && (nprot & PROT_WRITE)) in hpet_mmap()
405 *paddr = rman_get_start(sc->mem_res) + offset; in hpet_mmap()
431 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, in hpet_identify()
433 /* If found - let it be probed in normal way. */ in hpet_identify()
438 hpet->Address.Address, HPET_MEM_WIDTH); in hpet_identify()
441 /* If not - create it from table info. */ in hpet_identify()
447 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, in hpet_identify()
485 sc->dev = dev; in hpet_attach()
486 sc->handle = acpi_get_handle(dev); in hpet_attach()
488 sc->mem_rid = 0; in hpet_attach()
489 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, in hpet_attach()
491 if (sc->mem_res == NULL) in hpet_attach()
494 hpet_region_size = rman_get_size(sc->mem_res); in hpet_attach()
499 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); in hpet_attach()
507 val = bus_read_4(sc->mem_res, HPET_PERIOD); in hpet_attach()
511 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); in hpet_attach()
515 sc->freq = (1000000000000000LL + val / 2) / val; in hpet_attach()
516 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); in hpet_attach()
517 vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16; in hpet_attach()
518 rev = sc->caps & HPET_CAP_REV_ID; in hpet_attach()
519 num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8); in hpet_attach()
521 * ATI/AMD violates IA-PC HPET (High Precision Event Timers) in hpet_attach()
527 num_timers--; in hpet_attach()
536 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); in hpet_attach()
540 sc->num_timers = num_timers; in hpet_attach()
544 vendor, rev, sc->freq, in hpet_attach()
545 (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", in hpet_attach()
547 (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : ""); in hpet_attach()
550 t = &sc->t[i]; in hpet_attach()
551 t->sc = sc; in hpet_attach()
552 t->num = i; in hpet_attach()
553 t->mode = TIMER_STOPPED; in hpet_attach()
554 t->intr_rid = -1; in hpet_attach()
555 t->irq = -1; in hpet_attach()
556 t->pcpu_cpu = -1; in hpet_attach()
557 t->pcpu_misrouted = 0; in hpet_attach()
558 t->pcpu_master = -1; in hpet_attach()
559 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); in hpet_attach()
560 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); in hpet_attach()
563 " t%d: irqs 0x%08x (%d)%s%s%s\n", i, in hpet_attach()
564 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, in hpet_attach()
565 (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", in hpet_attach()
566 (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", in hpet_attach()
567 (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); in hpet_attach()
576 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); in hpet_attach()
578 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); in hpet_attach()
582 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); in hpet_attach()
587 sc->tc.tc_get_timecount = hpet_get_timecount, in hpet_attach()
588 sc->tc.tc_counter_mask = ~0u, in hpet_attach()
589 sc->tc.tc_name = "HPET", in hpet_attach()
590 sc->tc.tc_quality = 950, in hpet_attach()
591 sc->tc.tc_frequency = sc->freq; in hpet_attach()
592 sc->tc.tc_priv = sc; in hpet_attach()
593 sc->tc.tc_fill_vdso_timehands = hpet_vdso_timehands; in hpet_attach()
595 sc->tc.tc_fill_vdso_timehands32 = hpet_vdso_timehands32; in hpet_attach()
597 tc_init(&sc->tc); in hpet_attach()
599 /* If not disabled - setup and announce event timers. */ in hpet_attach()
605 sc->legacy_route = 0; in hpet_attach()
607 "legacy_route", &sc->legacy_route); in hpet_attach()
608 if ((sc->caps & HPET_CAP_LEG_RT) == 0) in hpet_attach()
609 sc->legacy_route = 0; in hpet_attach()
610 if (sc->legacy_route) { in hpet_attach()
611 sc->t[0].vectors = 0; in hpet_attach()
612 sc->t[1].vectors = 0; in hpet_attach()
615 /* Check what IRQs we want use. */ in hpet_attach()
616 /* By default allow any PCI IRQs. */ in hpet_attach()
617 sc->allowed_irqs = 0xffff0000; in hpet_attach()
619 * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 in hpet_attach()
622 * properly, that makes it very unreliable - it freezes after any in hpet_attach()
623 * interrupt loss. Avoid legacy IRQs for AMD. in hpet_attach()
627 sc->allowed_irqs = 0x00000000; in hpet_attach()
633 sc->allowed_irqs = 0x00000000; in hpet_attach()
635 * ServerWorks HT1000 reported to have problems with IRQs >= 16. in hpet_attach()
636 * Lower IRQs are working, but allowed mask is not set correctly. in hpet_attach()
640 sc->allowed_irqs = 0x00000000; in hpet_attach()
642 * Neither QEMU nor VirtualBox report supported IRQs correctly. in hpet_attach()
643 * The only way to use HPET there is to specify IRQs manually in hpet_attach()
647 sc->allowed_irqs = 0x00000000; in hpet_attach()
650 "allowed_irqs", &sc->allowed_irqs); in hpet_attach()
652 /* Get how much per-CPU timers we should try to provide. */ in hpet_attach()
653 sc->per_cpu = 1; in hpet_attach()
655 "per_cpu", &sc->per_cpu); in hpet_attach()
658 sc->useirq = 0; in hpet_attach()
660 cvectors = sc->allowed_irqs & 0xffff0000; in hpet_attach()
661 dvectors = sc->allowed_irqs & 0x0000ffff; in hpet_attach()
662 if (sc->legacy_route) in hpet_attach()
665 t = &sc->t[i]; in hpet_attach()
666 if (sc->legacy_route && i < 2) in hpet_attach()
667 t->irq = (i == 0) ? 0 : 8; in hpet_attach()
669 else if (t->caps & HPET_TCAP_FSB_INT_DEL) { in hpet_attach()
672 &t->irq))) { in hpet_attach()
679 else if (dvectors & t->vectors) { in hpet_attach()
680 t->irq = ffs(dvectors & t->vectors) - 1; in hpet_attach()
681 dvectors &= ~(1 << t->irq); in hpet_attach()
683 if (t->irq >= 0) { in hpet_attach()
684 t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq); in hpet_attach()
685 t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, in hpet_attach()
686 &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE); in hpet_attach()
687 if (t->intr_res == NULL) { in hpet_attach()
688 t->irq = -1; in hpet_attach()
690 "Can't map interrupt for t%d.\n", i); in hpet_attach()
691 } else if (bus_setup_intr(dev, t->intr_res, in hpet_attach()
693 &t->intr_handle) != 0) { in hpet_attach()
694 t->irq = -1; in hpet_attach()
698 bus_describe_intr(dev, t->intr_res, in hpet_attach()
699 t->intr_handle, "t%d", i); in hpet_attach()
703 if (t->irq < 0 && (cvectors & t->vectors) != 0) { in hpet_attach()
704 cvectors &= t->vectors; in hpet_attach()
705 sc->useirq |= (1 << i); in hpet_attach()
708 if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0) in hpet_attach()
709 sc->legacy_route = 0; in hpet_attach()
710 if (sc->legacy_route) in hpet_attach()
712 /* Group timers for per-CPU operation. */ in hpet_attach()
713 num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu); in hpet_attach()
718 t = &sc->t[i]; in hpet_attach()
719 if (t->irq >= 0 && num_percpu_t > 0) { in hpet_attach()
722 t->pcpu_cpu = cur_cpu; in hpet_attach()
723 t->pcpu_master = pcpu_master; in hpet_attach()
724 sc->t[pcpu_master]. in hpet_attach()
726 bus_bind_intr(dev, t->intr_res, cur_cpu); in hpet_attach()
728 num_percpu_t--; in hpet_attach()
729 } else if (t->irq >= 0) in hpet_attach()
730 bus_bind_intr(dev, t->intr_res, CPU_FIRST()); in hpet_attach()
732 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); in hpet_attach()
733 sc->irq = -1; in hpet_attach()
734 /* If at least one timer needs legacy IRQ - set it up. */ in hpet_attach()
735 if (sc->useirq) { in hpet_attach()
736 j = i = fls(cvectors) - 1; in hpet_attach()
737 while (j > 0 && (cvectors & (1 << (j - 1))) != 0) in hpet_attach()
738 j--; in hpet_attach()
739 sc->intr_rid = hpet_find_irq_rid(dev, j, i); in hpet_attach()
740 sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, in hpet_attach()
741 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE); in hpet_attach()
742 if (sc->intr_res == NULL) in hpet_attach()
743 device_printf(dev, "Can't map interrupt.\n"); in hpet_attach()
744 else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK, in hpet_attach()
745 hpet_intr, NULL, sc, &sc->intr_handle) != 0) { in hpet_attach()
748 sc->irq = rman_get_start(sc->intr_res); in hpet_attach()
750 bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); in hpet_attach()
755 t = &sc->t[i]; in hpet_attach()
756 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); in hpet_attach()
757 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); in hpet_attach()
758 t->caps &= ~(HPET_TCNF_INT_TYPE); in hpet_attach()
759 t->caps |= HPET_TCNF_32MODE; in hpet_attach()
760 if (t->irq >= 0 && sc->legacy_route && i < 2) { in hpet_attach()
764 if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) { in hpet_attach()
770 t->irq, &addr, &data) == 0) { in hpet_attach()
771 bus_write_4(sc->mem_res, in hpet_attach()
773 bus_write_4(sc->mem_res, in hpet_attach()
775 t->caps |= HPET_TCNF_FSB_EN; in hpet_attach()
777 t->irq = -2; in hpet_attach()
780 if (t->irq >= 0) in hpet_attach()
781 t->caps |= (t->irq << 9); in hpet_attach()
782 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) in hpet_attach()
783 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; in hpet_attach()
784 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); in hpet_attach()
786 if (t->irq < 0 && in hpet_attach()
787 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) in hpet_attach()
791 t->et.et_name = "HPET"; in hpet_attach()
793 sprintf(t->name, "HPET%d", maxhpetet); in hpet_attach()
794 t->et.et_name = t->name; in hpet_attach()
796 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; in hpet_attach()
797 t->et.et_quality = 450; in hpet_attach()
798 if (t->pcpu_master >= 0) { in hpet_attach()
799 t->et.et_flags |= ET_FLAGS_PERCPU; in hpet_attach()
800 t->et.et_quality += 100; in hpet_attach()
802 t->et.et_quality -= 100; in hpet_attach()
803 if ((t->caps & HPET_TCAP_PER_INT) == 0) in hpet_attach()
804 t->et.et_quality -= 10; in hpet_attach()
805 t->et.et_frequency = sc->freq; in hpet_attach()
806 t->et.et_min_period = in hpet_attach()
807 ((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq; in hpet_attach()
808 t->et.et_max_period = (0xfffffffeLLU << 32) / sc->freq; in hpet_attach()
809 t->et.et_start = hpet_start; in hpet_attach()
810 t->et.et_stop = hpet_stop; in hpet_attach()
811 t->et.et_priv = &sc->t[i]; in hpet_attach()
812 if (t->pcpu_master < 0 || t->pcpu_master == i) { in hpet_attach()
813 et_register(&t->et); in hpet_attach()
817 acpi_GetInteger(sc->handle, "_UID", &sc->acpi_uid); in hpet_attach()
825 error = make_dev_s(&mda, &sc->pdev, "hpet%d", device_get_unit(dev)); in hpet_attach()
827 sc->mmap_allow = 1; in hpet_attach()
829 &sc->mmap_allow); in hpet_attach()
830 sc->mmap_allow_write = 0; in hpet_attach()
832 &sc->mmap_allow_write); in hpet_attach()
836 CTLFLAG_RW, &sc->mmap_allow, 0, in hpet_attach()
837 "Allow userland to memory map HPET"); in hpet_attach()
841 CTLFLAG_RW, &sc->mmap_allow_write, 0, in hpet_attach()
883 /* Re-enable the timer after a resume to keep the clock advancing. */ in hpet_resume()
887 for (i = 0; i < sc->num_timers; i++) { in hpet_resume()
888 t = &sc->t[i]; in hpet_resume()
890 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) { in hpet_resume()
896 t->irq, &addr, &data) == 0) { in hpet_resume()
897 bus_write_4(sc->mem_res, in hpet_resume()
899 bus_write_4(sc->mem_res, in hpet_resume()
904 if (t->mode == TIMER_STOPPED) in hpet_resume()
906 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); in hpet_resume()
907 if (t->mode == TIMER_PERIODIC && in hpet_resume()
908 (t->caps & HPET_TCAP_PER_INT) != 0) { in hpet_resume()
909 t->caps |= HPET_TCNF_TYPE; in hpet_resume()
910 t->next += t->div; in hpet_resume()
911 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), in hpet_resume()
912 t->caps | HPET_TCNF_VAL_SET); in hpet_resume()
913 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), in hpet_resume()
914 t->next); in hpet_resume()
915 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); in hpet_resume()
916 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), in hpet_resume()
917 t->div); in hpet_resume()
919 t->next += sc->freq / 1024; in hpet_resume()
920 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), in hpet_resume()
921 t->next); in hpet_resume()
923 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); in hpet_resume()
924 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); in hpet_resume()
941 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); in hpet_test()
943 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); in hpet_test()
945 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); in hpet_test()
952 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", in hpet_test()
953 (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); in hpet_test()
955 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); in hpet_test()
968 for (i = 0; i < sc->num_timers; i++) { in hpet_remap_intr()
969 t = &sc->t[i]; in hpet_remap_intr()
970 if (t->irq != irq) in hpet_remap_intr()
978 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); in hpet_remap_intr()
979 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); in hpet_remap_intr()