Lines Matching +full:0 +full:x028

75 # define ARMV7_NEON      (1<<0)
103 # define ARM_CPU_IMP_ARM           0x41
104 # define HISI_CPU_IMP              0x48
105 # define ARM_CPU_IMP_APPLE         0x61
106 # define ARM_CPU_IMP_MICROSOFT     0x6D
107 # define ARM_CPU_IMP_AMPERE        0xC0
109 # define ARM_CPU_PART_CORTEX_A72   0xD08
110 # define ARM_CPU_PART_N1           0xD0C
111 # define ARM_CPU_PART_V1           0xD40
112 # define ARM_CPU_PART_N2           0xD49
113 # define HISI_CPU_PART_KP920       0xD01
114 # define ARM_CPU_PART_V2           0xD4F
116 # define APPLE_CPU_PART_M1_ICESTORM         0x022
117 # define APPLE_CPU_PART_M1_FIRESTORM        0x023
118 # define APPLE_CPU_PART_M1_ICESTORM_PRO     0x024
119 # define APPLE_CPU_PART_M1_FIRESTORM_PRO    0x025
120 # define APPLE_CPU_PART_M1_ICESTORM_MAX     0x028
121 # define APPLE_CPU_PART_M1_FIRESTORM_MAX    0x029
122 # define APPLE_CPU_PART_M2_BLIZZARD         0x032
123 # define APPLE_CPU_PART_M2_AVALANCHE        0x033
124 # define APPLE_CPU_PART_M2_BLIZZARD_PRO     0x034
125 # define APPLE_CPU_PART_M2_AVALANCHE_PRO    0x035
126 # define APPLE_CPU_PART_M2_BLIZZARD_MAX     0x038
127 # define APPLE_CPU_PART_M2_AVALANCHE_MAX    0x039
129 # define MICROSOFT_CPU_PART_COBALT_100      0xD49
132 # define MIDR_PARTNUM_MASK        (0xfffU << MIDR_PARTNUM_SHIFT)
137 # define MIDR_IMPLEMENTER_MASK    (0xffU << MIDR_IMPLEMENTER_SHIFT)
142 # define MIDR_ARCHITECTURE_MASK   (0xfU << MIDR_ARCHITECTURE_SHIFT)
153             (0xfU      << MIDR_ARCHITECTURE_SHIFT) | \
171 #   define GNU_PROPERTY_AARCH64_BTI (1 << 0)   /* Has Branch Target Identification */
174 #   define GNU_PROPERTY_AARCH64_BTI 0  /* No Branch Target Identification */
191 #   define GNU_PROPERTY_AARCH64_POINTER_AUTH 0  /* No Pointer Authentication */
192 #   if GNU_PROPERTY_AARCH64_BTI != 0
200 #  if GNU_PROPERTY_AARCH64_POINTER_AUTH != 0 || GNU_PROPERTY_AARCH64_BTI != 0
204     .long 0x10;
205     .long 0x5;
207     .long 0xc0000000; /* GNU_PROPERTY_AARCH64_FEATURE_1_AND */
210     .long 0;