Lines Matching +full:cortex +full:- +full:r5

1 /* Do not modify. This file is auto-generated from sha512-armv4.pl. */
2 @ Copyright 2007-2020 The OpenSSL Project Authors. All Rights Reserved.
22 @ by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue
27 @ Rescheduling for dual-issue pipeline resulted in 6% improvement on
28 @ Cortex A8 core and ~40 cycles per processed byte.
32 @ Profiler-assisted and platform-specific optimization resulted in 7%
37 @ Add NEON implementation. On Cortex A8 it was measured to process
38 @ one byte in 23.3 cycles or ~60% faster than integer-only code.
44 @ Technical writers asserted that 3-way S4 pipeline can sustain
46 @ not be observed, see http://www.openssl.org/~appro/Snapdragon-S4.html
47 @ for further details. On side note Cortex-A15 processes one byte in
53 @ h[0-7], namely with most significant dword at *lower* address, which
55 @ expected to maintain native byte order for whole 64-bit values.
58 # define VFP_ABI_PUSH	vstmdb	sp!,{d8-d15}
59 # define VFP_ABI_POP	vldmia	sp!,{d8-d15}
130 .size	K512,.-K512
136 .word	OPENSSL_armcap_P-.Lsha512_block_data_order
138 .skip	32-4
164 	stmdb	sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
179 	ldr	r5,[r0,#0+LO]
255 	str	r5,[sp,#0+0]
283 	mov	r9,r5,lsr#28
286 	eor	r10,r10,r5,lsl#4
288 	eor	r10,r10,r5,lsr#2
289 	eor	r9,r9,r5,lsl#30
292 	eor	r10,r10,r5,lsr#7
293 	eor	r9,r9,r5,lsl#25
296 	and	r9,r5,r11
300 	orr	r5,r5,r11
302 	and	r5,r5,r12
305 	orr	r5,r5,r9		@ Maj(a,b,c).lo
307 	adds	r5,r5,r3
395 	str	r5,[sp,#0+0]
423 	mov	r9,r5,lsr#28
426 	eor	r10,r10,r5,lsl#4
428 	eor	r10,r10,r5,lsr#2
429 	eor	r9,r9,r5,lsl#30
432 	eor	r10,r10,r5,lsr#7
433 	eor	r9,r9,r5,lsl#25
436 	and	r9,r5,r11
440 	orr	r5,r5,r11
442 	and	r5,r5,r12
445 	orr	r5,r5,r9		@ Maj(a,b,c).lo
447 	adds	r5,r5,r3
467 	adds	r9,r5,r9
476 	ldr	r5,[sp,#16+0]
484 	adds	r9,r5,r9
508 	ldr	r5,[sp,#48+0]
516 	adds	r9,r5,r9
533 	ldmia	sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,pc}
535 	ldmia	sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
538 .word	0xe12fff1e			@ interoperable with Thumb ISA:-)
540 .size	sha512_block_data_order,.-sha512_block_data_order
542 .arch	armv7-a
550 	dmb	@ errata #451034 on early Cortex A8
1870 .size	sha512_block_data_order_neon,.-sha512_block_data_order_neon