Lines Matching +full:0 +full:x03ffffff
23 cmp r1,#0
24 str r3,[r0,#0] @ zero hash value
35 moveq r0,#0
42 ldrb r4,[r1,#0]
43 mov r10,#0x0fffffff
45 and r3,r10,#-4 @ 0x0ffffffc
103 str r4,[r0,#0]
114 mov r0,#0
123 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
135 cmp r3,#0
217 adc r8,r8,#0
227 str r0,[sp,#0] @ future r4
232 adc lr,r3,#0 @ future r6
246 ldr r4,[sp,#0]
252 adc r1,r1,#0
255 adc r3,r3,#0
262 adcs r5,r5,#0
263 adcs r6,r6,#0
264 adcs r7,r7,#0
265 adc r8,r8,#0
281 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
293 adcs r9,r4,#0
294 adcs r10,r5,#0
295 adcs r11,r6,#0
296 adc r7,r7,#0
303 ldr r8,[r2,#0]
332 str r3,[r1,#0]
337 strb r3,[r1,#0]
375 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
389 and r2,r4,#0x03ffffff @ base 2^32 -> base 2^26
397 and r3,r3,#0x03ffffff
398 and r4,r4,#0x03ffffff
399 and r5,r5,#0x03ffffff
472 @ >>+ denotes Hnext += Hn>>26, Hn &= 0x3ffffff. This means that
509 vbic.i32 d16,#0xfc000000 @ &=0x03ffffff
511 vbic.i32 d10,#0xfc000000
518 vbic.i32 d18,#0xfc000000
519 vbic.i32 d12,#0xfc000000
527 vbic.i32 d14,#0xfc000000
530 vbic.i32 d10,#0xfc000000
532 vbic.i32 d16,#0xfc000000
539 add r6,r0,#(48+0*9*4)
557 vst4.32 {d0[0],d1[0],d2[0],d3[0]},[r6]!
559 vst4.32 {d4[0],d5[0],d6[0],d7[0]},[r6]!
561 vst1.32 {d8[0]},[r6,:32]
585 vst4.32 {d0[0],d1[0],d2[0],d3[0]},[r6]!
587 vst4.32 {d4[0],d5[0],d6[0],d7[0]},[r6]!
589 vst1.32 {d8[0]},[r6]
618 ldr r4,[r0,#0] @ load hash value base 2^32
624 and r2,r4,#0x03ffffff @ base 2^32 -> base 2^26
636 and r3,r3,#0x03ffffff
639 and r4,r4,#0x03ffffff
641 and r5,r5,#0x03ffffff
644 vmov.32 d10[0],r2
645 vmov.32 d12[0],r3
646 vmov.32 d14[0],r4
647 vmov.32 d16[0],r5
648 vmov.32 d18[0],r6
664 vld4.32 {d10[0],d12[0],d14[0],d16[0]},[r0]!
666 vld1.32 {d18[0]},[r0]
675 vld4.32 {d20[0],d22[0],d24[0],d26[0]},[r1]!
676 vmov.32 d28[0],r3
693 vbic.i32 d26,#0xfc000000
697 vbic.i32 d24,#0xfc000000
701 vbic.i32 d20,#0xfc000000
702 vbic.i32 d22,#0xfc000000
721 vld4.32 {d20,d22,d24,d26},[r1] @ inp[0:1]
723 vld4.32 {d21,d23,d25,d27},[r4] @ inp[2:3] (or 0)
741 vbic.i32 q13,#0xfc000000
745 vbic.i32 q12,#0xfc000000
748 vbic.i32 q10,#0xfc000000
749 vbic.i32 q11,#0xfc000000
754 vld4.32 {d0[0],d1[0],d2[0],d3[0]},[r6]! @ load r^4
756 vld4.32 {d4[0],d5[0],d6[0],d7[0]},[r6]!
762 @ ((inp[0]*r^4+inp[2]*r^2+inp[4])*r^4+inp[6]*r^2
765 @ ((inp[0]*r^4+inp[2]*r^2+inp[4])*r^4+inp[6]*r^2+inp[8])*r^2
781 vadd.i32 d24,d24,d14 @ accumulate inp[0:1]
820 vld4.32 {d21,d23,d25,d27},[r4] @ inp[2:3] (or 0)
824 @ (hash+inp[0:1])*r^4 and accumulate
826 vmlal.u32 q8,d26,d0[0]
827 vmlal.u32 q5,d20,d0[0]
828 vmlal.u32 q9,d28,d0[0]
829 vmlal.u32 q6,d22,d0[0]
830 vmlal.u32 q7,d24,d0[0]
831 vld1.32 d8[0],[r6,:32]
833 vmlal.u32 q8,d24,d1[0]
834 vmlal.u32 q5,d28,d2[0]
835 vmlal.u32 q9,d26,d1[0]
836 vmlal.u32 q6,d20,d1[0]
837 vmlal.u32 q7,d22,d1[0]
839 vmlal.u32 q8,d22,d3[0]
840 vmlal.u32 q5,d26,d4[0]
841 vmlal.u32 q9,d24,d3[0]
842 vmlal.u32 q6,d28,d4[0]
843 vmlal.u32 q7,d20,d3[0]
845 vmlal.u32 q8,d20,d5[0]
846 vmlal.u32 q5,d24,d6[0]
847 vmlal.u32 q9,d22,d5[0]
848 vmlal.u32 q6,d26,d6[0]
849 vmlal.u32 q8,d28,d8[0]
851 vmlal.u32 q7,d28,d6[0]
852 vmlal.u32 q5,d22,d8[0]
853 vmlal.u32 q9,d20,d7[0]
855 vmlal.u32 q6,d24,d8[0]
856 vmlal.u32 q7,d26,d8[0]
858 vld4.32 {d20,d22,d24,d26},[r1] @ inp[0:1]
869 @ inp[0:3] previously loaded to q10-q13 and smashed to q10-q14.
876 vbic.i32 d16,#0xfc000000
880 vbic.i32 d10,#0xfc000000
888 vbic.i32 d18,#0xfc000000
890 vbic.i32 d12,#0xfc000000
894 vbic.i32 q13,#0xfc000000
901 vbic.i32 d14,#0xfc000000
902 vbic.i32 q12,#0xfc000000
907 vbic.i32 q10,#0xfc000000
909 vbic.i32 d16,#0xfc000000
910 vbic.i32 d10,#0xfc000000
913 vbic.i32 q11,#0xfc000000
919 @ multiply (inp[0:1]+hash) or inp[2:3] by r^2:r^1
921 add r7,r0,#(48+0*9*4)
925 movne r2,#0
936 vld4.32 {d0[0],d1[0],d2[0],d3[0]},[r6]! @ load r^2
952 vld4.32 {d4[0],d5[0],d6[0],d7[0]},[r6]!
960 vld1.32 d8[0],[r6,:32]
986 @ (hash+inp[0:1])*r^4:r^3 and accumulate
989 vld4.32 {d0[0],d1[0],d2[0],d3[0]},[r6]! @ load r^4
1000 vld4.32 {d4[0],d5[0],d6[0],d7[0]},[r6]!
1008 vld1.32 d8[0],[r6,:32]
1067 cmp r2,#0
1073 vst4.32 {d10[0],d12[0],d14[0],d16[0]},[r0]!
1074 vst1.32 {d18[0]},[r0]
1109 adcs r4,r4,#0
1110 adcs r5,r5,#0
1111 adcs r6,r6,#0
1112 adc r7,r7,#0
1115 adcs r9,r4,#0
1116 adcs r10,r5,#0
1117 adcs r11,r6,#0
1118 adc r7,r7,#0
1123 ldr r8,[r2,#0]
1145 str r3,[r1,#0] @ store the result
1156 .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1164 …9,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0