Lines Matching +full:cortex +full:- +full:r5
1 /* Do not modify. This file is auto-generated from bsaes-armv7.pl. */
2 @ Copyright 2012-2023 The OpenSSL Project Authors. All Rights Reserved.
20 @ Bit-sliced AES for ARM NEON
24 @ This implementation is direct adaptation of bsaes-x86_64 module for
25 @ ARM NEON. Except that this module is endian-neutral [in sense that
28 @ only low-level primitives and unsupported entry points, just enough
29 @ to collect performance results, which for Cortex-A8 core are:
31 @ encrypt 19.5 cycles per byte processed with 128-bit key
32 @ decrypt 22.1 cycles per byte processed with 128-bit key
33 @ key conv. 440 cycles per 128-bit key/0.18 of 8x block
37 @ http://www.openssl.org/~appro/Snapdragon-S4.html).
39 @ Cortex-A15 manages in 14.2/16.1 cycles [when integer-only code
43 @ [mostly] single-issue and thus can't [fully] benefit from
44 @ instruction-level parallelism. And when comparing to aes-armv4
46 @ bsaes-x86_64.pl for further details)...
50 @ April-August 2013
58 # define VFP_ABI_PUSH vstmdb sp!,{d8-d15}
59 # define VFP_ABI_POP vldmia sp!,{d8-d15}
76 .arch armv7-a
79 .syntax unified @ ARMv7-capable assembler is expected to handle this
97 add r6,r6,#.LM0ISR-_bsaes_decrypt8
200 sub r5,r5,#1
381 subs r5,r5,#1
383 @ multiplication by 0x05-0x00-0x04-0x00
554 .size _bsaes_decrypt8,.-_bsaes_decrypt8
578 .size _bsaes_const,.-_bsaes_const
588 sub r6,r6,#_bsaes_encrypt8-.LM0SR
693 sub r5,r5,#1
873 subs r5,r5,#1
1014 .size _bsaes_encrypt8,.-_bsaes_encrypt8
1023 sub r6,r6,#_bsaes_key_convert-.LM0
1039 sub r5,r5,#1
1066 subs r5,r5,#1
1067 vstmia r12!,{q0,q1,q2,q3,q4,q5,q6,q7} @ write bit-sliced round key
1073 .size _bsaes_key_convert,.-_bsaes_key_convert
1095 stmdb sp!, {r4,r5,r6,r7,r8,r9,r10, lr}
1106 add r12, #96 @ sifze of bit-slices key schedule
1110 mov r5, r10 @ pass # of rounds
1125 mov r5, r10 @ pass # of rounds
1154 mov r5, r10
1197 mov r5, r10
1341 ldmia sp!, {r4,r5,r6,r7,r8,r9,r10, pc}
1342 .size ossl_bsaes_cbc_encrypt,.-ossl_bsaes_cbc_encrypt
1352 stmdb sp!, {r4,r5,r6,r7,r8,r9,r10, lr}
1362 add r12, #96 @ size of bit-sliced key schedule
1366 mov r5, r10 @ pass # of rounds
1374 mov r8, #:lower16:(.LREVM0SR-.LM0)
1377 add r8, r6, #.LREVM0SR-.LM0 @ borrow r8
1388 mov r5, r10 @ pass # of rounds
1397 add r8, r6, #.LREVM0SR-.LM0 @ borrow r8
1424 @ to flip byte order in 32-bit counter
1433 mov r5, r10 @ pass rounds
1436 mov r6, #:lower16:(.LREVM0SR-.LSR)
1439 sub r6, r8, #.LREVM0SR-.LSR @ pass constants
1524 ldmia sp!, {r4,r5,r6,r7,r8,r9,r10, pc} @ return
1529 stmdb sp!, {r4,r5,r6,r7,r8, lr}
1532 mov r5, r1
1561 vst1.8 {q0}, [r5]! @ store output
1569 ldmia sp!, {r4,r5,r6,r7,r8, pc}
1570 .size ossl_bsaes_ctr32_encrypt_blocks,.-ossl_bsaes_ctr32_encrypt_blocks
1576 stmdb sp!, {r4,r5,r6,r7,r8,r9,r10, lr} @ 0x20
1605 @ add r12, #96 @ size of bit-sliced key schedule
1610 mov r5, r1 @ pass # of rounds
1623 mov r5, r1 @ pass # of rounds
1713 mov r5, r1 @ pass rounds
1825 mov r5, r1 @ pass rounds
1857 mov r5, r1 @ pass rounds
1892 mov r5, r1 @ pass rounds
1920 mov r5, r1 @ pass rounds
1945 mov r5, r1 @ pass rounds
1969 mov r5, r1 @ pass rounds
2007 ldrb r1, [r8, #-0x10]
2008 strb r0, [r8, #-0x10]
2047 ldmia sp!, {r4,r5,r6,r7,r8,r9,r10, pc} @ return
2049 .size ossl_bsaes_xts_encrypt,.-ossl_bsaes_xts_encrypt
2056 stmdb sp!, {r4,r5,r6,r7,r8,r9,r10, lr} @ 0x20
2085 @ add r12, #96 @ size of bit-sliced key schedule
2090 mov r5, r1 @ pass # of rounds
2106 mov r5, r1 @ pass # of rounds
2204 mov r5, r1 @ pass rounds
2316 mov r5, r1 @ pass rounds
2350 mov r5, r1 @ pass rounds
2379 mov r5, r1 @ pass rounds
2407 mov r5, r1 @ pass rounds
2432 mov r5, r1 @ pass rounds
2456 mov r5, r1 @ pass rounds
2474 mov r5, r2 @ preserve magic
2484 mov r2, r5
2558 ldmia sp!, {r4,r5,r6,r7,r8,r9,r10, pc} @ return
2560 .size ossl_bsaes_xts_decrypt,.-ossl_bsaes_xts_decrypt