Lines Matching +full:cortex +full:- +full:r5
1 /* Do not modify. This file is auto-generated from aes-armv4.pl. */
2 @ Copyright 2007-2020 The OpenSSL Project Authors. All Rights Reserved.
21 @ Code uses single 1K S-box and is >2 times faster than code generated
22 @ by gcc-3.4.1. This is thanks to unique feature of ARMv4 ISA, which
25 @ is endian-neutral. The performance is ~42 cycles/byte for 128-bit
26 @ key [on single-issue Xscale PXA250 core].
34 @ Rescheduling for dual-issue pipeline resulted in 12% improvement on
35 @ Cortex A8 core and ~25 cycles per byte processed with 128-bit key.
39 @ Profiler-assisted and platform-specific optimization resulted in 16%
40 @ improvement on Cortex A8 core and ~21.5 cycles per byte.
164 .size AES_Te,.-AES_Te
177 stmdb sp!,{r1,r4-r12,lr}
181 sub r10,r3,#AES_encrypt-AES_Te @ Te
186 ldrb r0,[r12,#3] @ load input data in endian-neutral
188 ldrb r5,[r12,#1]
192 orr r0,r0,r5,lsl#16
195 ldrb r5,[r12,#5]
199 orr r1,r1,r5,lsl#16
202 ldrb r5,[r12,#9]
206 orr r2,r2,r5,lsl#16
209 ldrb r5,[r12,#13]
212 orr r3,r3,r5,lsl#16
241 mov r4,r0,lsr#24 @ write output in endian-neutral
242 mov r5,r0,lsr#16 @ manner...
245 strb r5,[r12,#1]
248 mov r5,r1,lsr#16
252 strb r5,[r12,#5]
255 mov r5,r2,lsr#16
259 strb r5,[r12,#9]
262 mov r5,r3,lsr#16
266 strb r5,[r12,#13]
271 ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,pc}
273 ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
276 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
278 .size AES_encrypt,.-AES_encrypt
283 str lr,[sp,#-4]! @ push lr
284 ldmia r11!,{r4,r5,r6,r7}
286 ldr r12,[r11,#240-16]
287 eor r1,r1,r5
300 ldr r5,[r10,r8,lsl#2] @ Te2[s0>>8]
313 eor r5,r5,r8,ror#8
331 eor r2,r2,r5,ror#16
341 ldr r4,[r11,#-12]
344 ldr r5,[r11,#-8]
346 ldr r6,[r11,#-4]
350 eor r2,r2,r5
362 ldrb r5,[r10,r8,lsl#2] @ Te4[s0>>8]
375 eor r5,r8,r5,lsl#8
393 eor r2,r5,r2,lsl#24
404 ldr r5,[r11,#8]
410 eor r2,r2,r5
415 .size _armv4_AES_encrypt,.-_armv4_AES_encrypt
431 moveq r0,#-1
437 moveq r0,#-1
448 movne r0,#-1
451 .Lok: stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
459 sub r10,r3,#_armv4_AES_set_encrypt_key-AES_Te-1024 @ Te4
463 ldrb r0,[r12,#3] @ load input data in endian-neutral
465 ldrb r5,[r12,#1]
469 orr r0,r0,r5,lsl#16
472 ldrb r5,[r12,#5]
476 orr r1,r1,r5,lsl#16
479 ldrb r5,[r12,#9]
483 orr r2,r2,r5,lsl#16
486 ldrb r5,[r12,#13]
490 orr r3,r3,r5,lsl#16
491 str r1,[r11,#-12]
493 str r2,[r11,#-8]
494 str r3,[r11,#-4]
507 str r1,[r11,#-12]
508 str r2,[r11,#-8]
509 str r3,[r11,#-4]
515 str r12,[r11,#240-16]
520 and r5,lr,r3,lsr#24
522 ldrb r5,[r10,r5]
527 orr r5,r5,r7,lsl#24
529 orr r5,r5,r8,lsl#16
531 orr r5,r5,r9,lsl#8
532 eor r5,r5,r4
533 eor r0,r0,r5 @ rk[4]=rk[0]^...
537 str r1,[r11,#-12]
539 str r2,[r11,#-8]
541 str r3,[r11,#-4]
550 ldrb r5,[r12,#17]
554 orr r8,r8,r5,lsl#16
557 ldrb r5,[r12,#21]
560 orr r9,r9,r5,lsl#16
563 str r9,[r11,#-4]
572 str r9,[r11,#-4]
578 str r12,[r11,#240-24]
584 and r5,lr,r9,lsr#24
586 ldrb r5,[r10,r5]
591 orr r5,r5,r7,lsl#24
593 orr r5,r5,r8,lsl#16
595 orr r5,r5,r9,lsl#8
596 eor r9,r5,r4
601 str r1,[r11,#-20]
603 str r2,[r11,#-16]
605 str r3,[r11,#-12]
612 ldr r7,[r11,#-32]
613 ldr r8,[r11,#-28]
616 str r7,[r11,#-8]
617 str r9,[r11,#-4]
624 ldrb r5,[r12,#25]
628 orr r8,r8,r5,lsl#16
631 ldrb r5,[r12,#29]
634 orr r9,r9,r5,lsl#16
637 str r9,[r11,#-4]
646 str r9,[r11,#-4]
650 str r12,[r11,#240-32]
656 and r5,lr,r9,lsr#24
658 ldrb r5,[r10,r5]
663 orr r5,r5,r7,lsl#24
665 orr r5,r5,r8,lsl#16
667 orr r5,r5,r9,lsl#8
668 eor r9,r5,r4
673 str r1,[r11,#-28]
675 str r2,[r11,#-24]
677 str r3,[r11,#-20]
684 and r5,lr,r3
686 ldrb r5,[r10,r5]
691 orr r5,r5,r7,lsl#8
693 orr r5,r5,r8,lsl#16
694 ldr r4,[r11,#-48]
695 orr r5,r5,r9,lsl#24
697 ldr r7,[r11,#-44]
698 ldr r8,[r11,#-40]
699 eor r4,r4,r5 @ rk[12]=rk[4]^...
700 ldr r9,[r11,#-36]
702 str r4,[r11,#-16]
704 str r7,[r11,#-12]
706 str r8,[r11,#-8]
707 str r9,[r11,#-4]
712 ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
719 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
721 .size AES_set_encrypt_key,.-AES_set_encrypt_key
727 str lr,[sp,#-4]! @ push lr
736 .size AES_set_decrypt_key,.-AES_set_decrypt_key
744 stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
754 ldr r1,[r7,#-12]
755 ldr r2,[r7,#-8]
756 ldr r3,[r7,#-4]
757 ldr r4,[r8],#-16
758 ldr r5,[r8,#16+4]
761 str r0,[r10],#-16
766 str r5,[r11,#-12]
767 str r6,[r11,#-8]
768 str r9,[r11,#-4]
790 mov r12,r12,lsl#2 @ (rounds-1)*4
811 eor r5,r0,r3 @ tp9
814 eor r4,r4,r5,ror#24 @ ^= ROTATE(tpb=tp9^tp2,8)
816 eor r4,r4,r5,ror#16 @ ^= ROTATE(tpd=tp9^tp4,16)
817 eor r4,r4,r5,ror#8 @ ^= ROTATE(tp9,24)
826 ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,pc}
828 ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
831 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
833 .size AES_set_enc2dec_key,.-AES_set_enc2dec_key
935 .size AES_Td,.-AES_Td
948 stmdb sp!,{r1,r4-r12,lr}
952 sub r10,r3,#AES_decrypt-AES_Td @ Td
957 ldrb r0,[r12,#3] @ load input data in endian-neutral
959 ldrb r5,[r12,#1]
963 orr r0,r0,r5,lsl#16
966 ldrb r5,[r12,#5]
970 orr r1,r1,r5,lsl#16
973 ldrb r5,[r12,#9]
977 orr r2,r2,r5,lsl#16
980 ldrb r5,[r12,#13]
983 orr r3,r3,r5,lsl#16
1012 mov r4,r0,lsr#24 @ write output in endian-neutral
1013 mov r5,r0,lsr#16 @ manner...
1016 strb r5,[r12,#1]
1019 mov r5,r1,lsr#16
1023 strb r5,[r12,#5]
1026 mov r5,r2,lsr#16
1030 strb r5,[r12,#9]
1033 mov r5,r3,lsr#16
1037 strb r5,[r12,#13]
1042 ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,pc}
1044 ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
1047 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
1049 .size AES_decrypt,.-AES_decrypt
1054 str lr,[sp,#-4]! @ push lr
1055 ldmia r11!,{r4,r5,r6,r7}
1057 ldr r12,[r11,#240-16]
1058 eor r1,r1,r5
1071 ldr r5,[r10,r8,lsl#2] @ Td2[s0>>8]
1084 eor r5,r8,r5,ror#8
1102 eor r2,r2,r5,ror#8
1113 ldr r4,[r11,#-12]
1115 ldr r5,[r11,#-8]
1117 ldr r6,[r11,#-4]
1121 eor r2,r2,r5
1131 ldr r5,[r10,#0] @ prefetch Td4
1134 ldr r5,[r10,#96]
1137 ldr r5,[r10,#192]
1143 ldrb r5,[r10,r8] @ Td4[s0>>8]
1156 eor r5,r5,r8,lsl#8
1169 eor r2,r5,r2,lsl#16
1184 ldr r5,[r11,#8]
1190 eor r2,r2,r5
1195 .size _armv4_AES_decrypt,.-_armv4_AES_decrypt