Lines Matching +full:guest +full:- +full:index +full:- +full:bits
53 * Emulate the fault-causing instruction (if set in the event response flags).
54 * This will allow the guest to continue execution without lifting the page
79 * Currently only useful for MSR and control-register write events.
95 * At the moment x86-only, applies to EAX-EDX, ESP, EBP, ESI, EDI, R8-R15,
109 * Have a one-shot VM_EVENT_REASON_INTERRUPT event sent for the first
149 /* Single-step (e.g. MTF) */
160 * As this behavior is CPU-specific, users are advised to not rely on it.
171 /* Supported values for the vm_event_write_ctrlreg index. */
177 /* The limit field is right-shifted by 12 bits if .ar.g is set. */
222 * VM. npt_base is the guest physical address of the L1 hypervisors
223 * EPT/NPT tables for the nested guest.
225 * All bits outside of architectural address ranges are reserved for
279 * GLA_VALID: If the gla field holds a guest VA associated with the event
303 uint32_t index; member
319 uint64_t pending_dbg; /* Behaves like the VT-x PENDING_DBG field. */
339 uint32_t instr_info; /* VMX: VMCS Instruction-Information */
382 uint8_t data[sizeof(struct vm_event_regs_x86) - sizeof(uint32_t)];
435 * c-file-style: "BSD"
436 * c-basic-offset: 4
437 * tab-width: 4
438 * indent-tabs-mode: nil