Lines Matching +full:0 +full:x0010f000
34 #define TRC_GEN 0x0001f000 /* General trace */
35 #define TRC_SCHED 0x0002f000 /* Xen Scheduler trace */
36 #define TRC_DOM0OP 0x0004f000 /* Xen DOM0 operation trace */
37 #define TRC_HVM 0x0008f000 /* Xen HVM trace */
38 #define TRC_MEM 0x0010f000 /* Xen memory trace */
39 #define TRC_PV 0x0020f000 /* Xen PV traces */
40 #define TRC_SHADOW 0x0040f000 /* Xen shadow tracing */
41 #define TRC_HW 0x0080f000 /* Xen hardware-related traces */
42 #define TRC_GUEST 0x0800f000 /* Guest-generated traces */
43 #define TRC_ALL 0x0ffff000
44 #define TRC_HD_TO_EVENT(x) ((x)&0x0fffffff)
53 #define TRC_HVM_ENTRYEXIT 0x00081000 /* VMENTRY and #VMEXIT */
54 #define TRC_HVM_HANDLER 0x00082000 /* various HVM handlers */
55 #define TRC_HVM_EMUL 0x00084000 /* emulated devices */
57 #define TRC_SCHED_MIN 0x00021000 /* Just runstate changes */
58 #define TRC_SCHED_CLASS 0x00022000 /* Scheduler-specific */
59 #define TRC_SCHED_VERBOSE 0x00028000 /* More inclusive scheduling */
76 #define TRC_SCHED_CSCHED 0
90 #define TRC_DOM0_DOMOPS 0x00041000 /* Domains manipulations */
93 #define TRC_HW_PM 0x00801000 /* Power management traces */
94 #define TRC_HW_IRQ 0x00802000 /* Traces relating to the handling of IRQs */
133 #define TRC_PV_ENTRY 0x00201000 /* Hypervisor entry points for PV guests. */
134 #define TRC_PV_SUBCALL 0x00202000 /* Sub-call in a multicall hypercall */
162 * 0 bit 31 30|29 28|27 26|25 24|23 22|21 20|19 ... 0
175 #define TRC_PV_HYPERCALL_V2_ARG_32(i) (0x1 << (20 + 2*(i)))
176 #define TRC_PV_HYPERCALL_V2_ARG_64(i) (0x2 << (20 + 2*(i)))
177 #define TRC_PV_HYPERCALL_V2_ARG_MASK (0xfff00000)
196 #define TRC_HVM_NESTEDFLAG (0x400)
197 #define TRC_HVM_VMENTRY (TRC_HVM_ENTRYEXIT + 0x01)
198 #define TRC_HVM_VMEXIT (TRC_HVM_ENTRYEXIT + 0x02)
199 #define TRC_HVM_VMEXIT64 (TRC_HVM_ENTRYEXIT + TRC_64_FLAG + 0x02)
200 #define TRC_HVM_PF_XEN (TRC_HVM_HANDLER + 0x01)
201 #define TRC_HVM_PF_XEN64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x01)
202 #define TRC_HVM_PF_INJECT (TRC_HVM_HANDLER + 0x02)
203 #define TRC_HVM_PF_INJECT64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x02)
204 #define TRC_HVM_INJ_EXC (TRC_HVM_HANDLER + 0x03)
205 #define TRC_HVM_INJ_VIRQ (TRC_HVM_HANDLER + 0x04)
206 #define TRC_HVM_REINJ_VIRQ (TRC_HVM_HANDLER + 0x05)
207 #define TRC_HVM_IO_READ (TRC_HVM_HANDLER + 0x06)
208 #define TRC_HVM_IO_WRITE (TRC_HVM_HANDLER + 0x07)
209 #define TRC_HVM_CR_READ (TRC_HVM_HANDLER + 0x08)
210 #define TRC_HVM_CR_READ64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x08)
211 #define TRC_HVM_CR_WRITE (TRC_HVM_HANDLER + 0x09)
212 #define TRC_HVM_CR_WRITE64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x09)
213 #define TRC_HVM_DR_READ (TRC_HVM_HANDLER + 0x0A)
214 #define TRC_HVM_DR_WRITE (TRC_HVM_HANDLER + 0x0B)
215 #define TRC_HVM_MSR_READ (TRC_HVM_HANDLER + 0x0C)
216 #define TRC_HVM_MSR_WRITE (TRC_HVM_HANDLER + 0x0D)
217 #define TRC_HVM_CPUID (TRC_HVM_HANDLER + 0x0E)
218 #define TRC_HVM_INTR (TRC_HVM_HANDLER + 0x0F)
219 #define TRC_HVM_NMI (TRC_HVM_HANDLER + 0x10)
220 #define TRC_HVM_SMI (TRC_HVM_HANDLER + 0x11)
221 #define TRC_HVM_VMMCALL (TRC_HVM_HANDLER + 0x12)
222 #define TRC_HVM_HLT (TRC_HVM_HANDLER + 0x13)
223 #define TRC_HVM_INVLPG (TRC_HVM_HANDLER + 0x14)
224 #define TRC_HVM_INVLPG64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x14)
225 #define TRC_HVM_MCE (TRC_HVM_HANDLER + 0x15)
226 #define TRC_HVM_IOPORT_READ (TRC_HVM_HANDLER + 0x16)
227 #define TRC_HVM_IOMEM_READ (TRC_HVM_HANDLER + 0x17)
228 #define TRC_HVM_CLTS (TRC_HVM_HANDLER + 0x18)
229 #define TRC_HVM_LMSW (TRC_HVM_HANDLER + 0x19)
230 #define TRC_HVM_LMSW64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x19)
231 #define TRC_HVM_RDTSC (TRC_HVM_HANDLER + 0x1a)
232 #define TRC_HVM_INTR_WINDOW (TRC_HVM_HANDLER + 0x20)
233 #define TRC_HVM_NPF (TRC_HVM_HANDLER + 0x21)
234 #define TRC_HVM_REALMODE_EMULATE (TRC_HVM_HANDLER + 0x22)
235 #define TRC_HVM_TRAP (TRC_HVM_HANDLER + 0x23)
236 #define TRC_HVM_TRAP_DEBUG (TRC_HVM_HANDLER + 0x24)
237 #define TRC_HVM_VLAPIC (TRC_HVM_HANDLER + 0x25)
238 #define TRC_HVM_XCR_READ64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x26)
239 #define TRC_HVM_XCR_WRITE64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x27)
241 #define TRC_HVM_IOPORT_WRITE (TRC_HVM_HANDLER + 0x216)
242 #define TRC_HVM_IOMEM_WRITE (TRC_HVM_HANDLER + 0x217)
245 #define TRC_HVM_EMUL_HPET_START_TIMER (TRC_HVM_EMUL + 0x1)
246 #define TRC_HVM_EMUL_PIT_START_TIMER (TRC_HVM_EMUL + 0x2)
247 #define TRC_HVM_EMUL_RTC_START_TIMER (TRC_HVM_EMUL + 0x3)
248 #define TRC_HVM_EMUL_LAPIC_START_TIMER (TRC_HVM_EMUL + 0x4)
249 #define TRC_HVM_EMUL_HPET_STOP_TIMER (TRC_HVM_EMUL + 0x5)
250 #define TRC_HVM_EMUL_PIT_STOP_TIMER (TRC_HVM_EMUL + 0x6)
251 #define TRC_HVM_EMUL_RTC_STOP_TIMER (TRC_HVM_EMUL + 0x7)
252 #define TRC_HVM_EMUL_LAPIC_STOP_TIMER (TRC_HVM_EMUL + 0x8)
253 #define TRC_HVM_EMUL_PIT_TIMER_CB (TRC_HVM_EMUL + 0x9)
254 #define TRC_HVM_EMUL_LAPIC_TIMER_CB (TRC_HVM_EMUL + 0xA)
255 #define TRC_HVM_EMUL_PIC_INT_OUTPUT (TRC_HVM_EMUL + 0xB)
256 #define TRC_HVM_EMUL_PIC_KICK (TRC_HVM_EMUL + 0xC)
257 #define TRC_HVM_EMUL_PIC_INTACK (TRC_HVM_EMUL + 0xD)
258 #define TRC_HVM_EMUL_PIC_POSEDGE (TRC_HVM_EMUL + 0xE)
259 #define TRC_HVM_EMUL_PIC_NEGEDGE (TRC_HVM_EMUL + 0xF)
260 #define TRC_HVM_EMUL_PIC_PEND_IRQ_CALL (TRC_HVM_EMUL + 0x10)
261 #define TRC_HVM_EMUL_LAPIC_PIC_INTR (TRC_HVM_EMUL + 0x11)
264 #define TRC_PM_FREQ_CHANGE (TRC_HW_PM + 0x01)
265 #define TRC_PM_IDLE_ENTRY (TRC_HW_PM + 0x02)
266 #define TRC_PM_IDLE_EXIT (TRC_HW_PM + 0x03)
269 #define TRC_HW_IRQ_MOVE_CLEANUP_DELAY (TRC_HW_IRQ + 0x1)
270 #define TRC_HW_IRQ_MOVE_CLEANUP (TRC_HW_IRQ + 0x2)
271 #define TRC_HW_IRQ_BIND_VECTOR (TRC_HW_IRQ + 0x3)
272 #define TRC_HW_IRQ_CLEAR_VECTOR (TRC_HW_IRQ + 0x4)
273 #define TRC_HW_IRQ_MOVE_FINISH (TRC_HW_IRQ + 0x5)
274 #define TRC_HW_IRQ_ASSIGN_VECTOR (TRC_HW_IRQ + 0x6)
275 #define TRC_HW_IRQ_UNMAPPED_VECTOR (TRC_HW_IRQ + 0x7)
276 #define TRC_HW_IRQ_HANDLED (TRC_HW_IRQ + 0x8)
285 #define TRC_64_FLAG 0x100 /* Addresses are 64 bits (instead of 32 bits) */
310 * 0 <= cons < 2*X
311 * 0 <= prod < 2*X