Lines Matching +full:non +full:- +full:safety
51 * How should CPU0 event-channel notifications be delivered?
53 * If val == 0 then CPU0 event-channel notifications are not delivered.
79 * val[15:8] is interrupt flag of the PPI used by event-channel:
82 * val[7:0] is a PPI number used by event-channel.
91 * These are not used by Xen. They are here for convenience of HVM-guest
106 …* (See http://download.microsoft.com/download/A/B/4/AB43A34E-BDD0-4FA6-BDEF-79EEF16E880B/Hyperviso…
116 * - Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL)
117 * - APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
118 * - Virtual Processor index MSR (HV_X64_MSR_VP_INDEX)
119 * - Timer frequency MSRs (HV_X64_MSR_TSC_FREQUENCY and
208 * delivered at some non-zero rate, if we detect missed ticks then the
221 /* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */
224 /* Identity-map page directory used by Intel EPT when CR0.PG=0. */
243 * - 0: default, use the old addresses
245 * - 1: use the new default qemu addresses
268 * mixed: allow access to all altp2m ops for both in-guest and external tools
272 * Note that 'mixed' mode has not been evaluated for safety from a
274 * security-critical environment, each subop should be evaluated for
275 * safety, with unsafe subops blacklisted in XSM.
290 * 8: save/restore 64-bit FIP/FDP and clear FCS/FDS (default if CPU
293 * 4: save/restore 32-bit FIP/FDP, FCS/FDS, and clear upper 32-bits of