Lines Matching +full:guest +full:- +full:index +full:- +full:bits

51  * How should CPU0 event-channel notifications be delivered?
53  * If val == 0 then CPU0 event-channel notifications are not delivered.
79  * val[15:8] is interrupt flag of the PPI used by event-channel:
82  * val[7:0] is a PPI number used by event-channel.
91  * These are not used by Xen. They are here for convenience of HVM-guest
106 …* (See http://download.microsoft.com/download/A/B/4/AB43A34E-BDD0-4FA6-BDEF-79EEF16E880B/Hyperviso…
108  * To expose viridian enlightenments to the guest set this parameter
116  * - Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL)
117  * - APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
118  * - Virtual Processor index MSR (HV_X64_MSR_VP_INDEX)
119  * - Timer frequency MSRs (HV_X64_MSR_TSC_FREQUENCY and
204  *   As above, missed interrupts are delivered, but guest time always tracks
208  *   delivered at some non-zero rate, if we detect missed ticks then the
213  *   Guest time always tracks wallclock (i.e., real) time.
221 /* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */
224 /* Identity-map page directory used by Intel EPT when CR0.PG=0. */
243  *   - 0: default, use the old addresses
245  *   - 1: use the new default qemu addresses
262 /* Location of the VM Generation ID in guest physical address space. */
268  *  mixed: allow access to all altp2m ops for both in-guest and external tools
270  *  limited: guest only has limited access (ie. control VMFUNC and #VE)
274  * security-critical environment, each subop should be evaluated for
290  * 8: save/restore 64-bit FIP/FDP and clear FCS/FDS (default if CPU
293  * 4: save/restore 32-bit FIP/FDP, FCS/FDS, and clear upper 32-bits of
307  * the low 32 bits, while the size is in the high 32 ones.