Lines Matching +full:tsc +full:- +full:irq

3  * be saved along with the domain's memory and device-model state.
43     uint32_t gtsc_khz;        /* Guest's TSC frequency in kHz */
53  *     - Pre-3.4 didn't have msr_tsc_aux
54  *     - Pre-4.7 didn't have fpu_initialised
149     uint64_t tsc;  member
263     uint64_t tsc;  member
291          * be able to do the modification in-place.  in _hvm_hw_fix_cpu()
293         ucpu->nat.error_code = ucpu->cmp.error_code;  in _hvm_hw_fix_cpu()
294         ucpu->nat.pending_event = ucpu->cmp.pending_event;  in _hvm_hw_fix_cpu()
295         ucpu->nat.tsc = ucpu->cmp.tsc;  in _hvm_hw_fix_cpu()
296         ucpu->nat.msr_tsc_aux = 0;  in _hvm_hw_fix_cpu()
299     ucpu->nat.flags = XEN_X86_FPU_INITIALISED;  in _hvm_hw_fix_cpu()
317     /* Line IRx maps to IRQ irq_base+x */
321      * Where are we in ICW2-4 initialisation (0 means no init in progress)?
322      * Bits 0-1 (=x): Next write at A=1 sets ICW(x+1).
340     /* Automatically rotate IRQ priorities during AEOI? */
343     /* Exclude slave inputs when considering in-service IRQs? */
363  * IO-APIC
384 #define VIOAPIC_NUM_PINS  48 /* 16 ISA IRQs, 32 non-legacy PCI IRQS. */
445      * Indexed by ISA IRQ (assumes no ISA-device IRQ sharing).
457      * PCI-ISA interrupt router.
458      * Each PCI <device:INTx#> is 'wire-ORed' into one of four links using
502     /* Index register for 2-part operations */
518     /* Memory-mapped, software visible registers */
533     uint64_t res5[4*(24-HPET_TIMER_NUM)];  /* reserved, up to 0x3ff */
547     uint32_t tmr_val;   /* PM_TMR_BLK.TMR_VAL: 32bit free-running counter */
586         } xsave_hdr;                    /* The 64-byte header */
644 /* Range 22 - 34 (inclusive) reserved for Amazon */
647  * Largest type-code in use
656  * c-file-style: "BSD"
657  * c-basic-offset: 4
658  * tab-width: 4
659  * indent-tabs-mode: nil