Lines Matching +full:light +full:- +full:weight
2 * arch-x86/cpufeatureset.h
32 * Simply #include <public/arch-x86/cpufeatureset.h>
78 * first space in the comment immediately following the feature value. Note -
91 * Lower case => Can be opted-in to, but not available by default.
94 /* Intel-defined CPU features, CPUID level 0x00000001.edx, word 0 */
100 XEN_CPUFEATURE(MSR, 0*32+ 5) /*A Model-Specific Registers, RDMSR, WRMSR */
111 XEN_CPUFEATURE(PSE36, 0*32+17) /*S 36-bit PSEs */
118 XEN_CPUFEATURE(SSE2, 0*32+26) /*A Streaming SIMD Extensions-2 */
120 XEN_CPUFEATURE(HTT, 0*32+28) /*!A Hyper-Threading Technology */
124 /* Intel-defined CPU features, CPUID level 0x00000001.ecx, word 1 */
125 XEN_CPUFEATURE(SSE3, 1*32+ 0) /*A Streaming SIMD Extensions-3 */
126 XEN_CPUFEATURE(PCLMULQDQ, 1*32+ 1) /*A Carry-less multiplication */
127 XEN_CPUFEATURE(DTES64, 1*32+ 2) /* 64-bit Debug Store */
134 XEN_CPUFEATURE(SSSE3, 1*32+ 9) /*A Supplemental Streaming SIMD Extensions-3 */
151 XEN_CPUFEATURE(F16C, 1*32+29) /*A Half-precision convert instruction */
155 /* AMD-defined CPU features, CPUID level 0x80000001.edx, word 2 */
162 XEN_CPUFEATURE(LM, 2*32+29) /*A Long Mode (x86-64) */
166 /* AMD-defined CPU features, CPUID level 0x80000001.ecx, word 3 */
171 XEN_CPUFEATURE(CR8_LEGACY, 3*32+ 4) /*S CR8 in 32-bit mode */
173 XEN_CPUFEATURE(SSE4A, 3*32+ 6) /*A SSE-4A */
181 XEN_CPUFEATURE(LWP, 3*32+15) /* Light Weight Profiling */
189 /* Intel-defined CPU features, CPUID level 0x0000000D:1.eax, word 4 */
195 /* Intel-defined CPU features, CPUID level 0x00000007:0.ebx, word 5 */
212 XEN_CPUFEATURE(AVX512F, 5*32+16) /*A AVX-512 Foundation Instructions */
213 XEN_CPUFEATURE(AVX512DQ, 5*32+17) /*A AVX-512 Doubleword & Quadword Instrs */
217 XEN_CPUFEATURE(AVX512_IFMA, 5*32+21) /*A AVX-512 Integer Fused Multiply Add */
221 XEN_CPUFEATURE(AVX512PF, 5*32+26) /*A AVX-512 Prefetch Instructions */
222 XEN_CPUFEATURE(AVX512ER, 5*32+27) /*A AVX-512 Exponent & Reciprocal Instrs */
223 XEN_CPUFEATURE(AVX512CD, 5*32+28) /*A AVX-512 Conflict Detection Instrs */
225 XEN_CPUFEATURE(AVX512BW, 5*32+30) /*A AVX-512 Byte and Word Instructions */
226 XEN_CPUFEATURE(AVX512VL, 5*32+31) /*A AVX-512 Vector Length Extensions */
228 /* Intel-defined CPU features, CPUID level 0x00000007:0.ecx, word 6 */
230 XEN_CPUFEATURE(AVX512_VBMI, 6*32+ 1) /*A AVX-512 Vector Byte Manipulation Instrs */
234 XEN_CPUFEATURE(AVX512_VBMI2, 6*32+ 6) /*A Additional AVX-512 Vector Byte Manipulation Instrs */
235 XEN_CPUFEATURE(CET_SS, 6*32+ 7) /* CET - Shadow Stacks */
238 XEN_CPUFEATURE(VPCLMULQDQ, 6*32+10) /*A Vector Carry-less Multiplication Instrs */
249 /* AMD-defined CPU features, CPUID level 0x80000007.edx, word 7 */
253 /* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */
263 XEN_CPUFEATURE(IBRS_SAME_MODE, 8*32+19) /* IBRS provides same-mode protection */
271 /* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */
281 XEN_CPUFEATURE(CET_IBT, 9*32+20) /* CET - Indirect Branch Tracking */
289 /* Intel-defined CPU features, CPUID level 0x00000007:1.eax, word 10 */
290 XEN_CPUFEATURE(AVX_VNNI, 10*32+ 4) /*A AVX-VNNI Instructions */
292 XEN_CPUFEATURE(FZRM, 10*32+10) /*A Fast Zero-length REP MOVSB */
296 /* AMD-defined CPU features, CPUID level 0x80000021.eax, word 11 */
313 * c-file-style: "BSD"
314 * c-basic-offset: 4
315 * tab-width: 4
316 * indent-tabs-mode: nil