Lines Matching +full:32 +full:-
2 * arch-x86/cpufeatureset.h
32 * Simply #include <public/arch-x86/cpufeatureset.h>
64 * 32bit words.
78 * first space in the comment immediately following the feature value. Note -
91 * Lower case => Can be opted-in to, but not available by default.
94 /* Intel-defined CPU features, CPUID level 0x00000001.edx, word 0 */
95 XEN_CPUFEATURE(FPU, 0*32+ 0) /*A Onboard FPU */
96 XEN_CPUFEATURE(VME, 0*32+ 1) /*S Virtual Mode Extensions */
97 XEN_CPUFEATURE(DE, 0*32+ 2) /*A Debugging Extensions */
98 XEN_CPUFEATURE(PSE, 0*32+ 3) /*S Page Size Extensions */
99 XEN_CPUFEATURE(TSC, 0*32+ 4) /*A Time Stamp Counter */
100 XEN_CPUFEATURE(MSR, 0*32+ 5) /*A Model-Specific Registers, RDMSR, WRMSR */
101 XEN_CPUFEATURE(PAE, 0*32+ 6) /*A Physical Address Extensions */
102 XEN_CPUFEATURE(MCE, 0*32+ 7) /*A Machine Check Architecture */
103 XEN_CPUFEATURE(CX8, 0*32+ 8) /*A CMPXCHG8 instruction */
104 XEN_CPUFEATURE(APIC, 0*32+ 9) /*!A Onboard APIC */
105 XEN_CPUFEATURE(SEP, 0*32+11) /*A SYSENTER/SYSEXIT */
106 XEN_CPUFEATURE(MTRR, 0*32+12) /*S Memory Type Range Registers */
107 XEN_CPUFEATURE(PGE, 0*32+13) /*S Page Global Enable */
108 XEN_CPUFEATURE(MCA, 0*32+14) /*A Machine Check Architecture */
109 XEN_CPUFEATURE(CMOV, 0*32+15) /*A CMOV instruction (FCMOVCC and FCOMI too if FPU present)…
110 XEN_CPUFEATURE(PAT, 0*32+16) /*A Page Attribute Table */
111 XEN_CPUFEATURE(PSE36, 0*32+17) /*S 36-bit PSEs */
112 XEN_CPUFEATURE(CLFLUSH, 0*32+19) /*A CLFLUSH instruction */
113 XEN_CPUFEATURE(DS, 0*32+21) /* Debug Store */
114 XEN_CPUFEATURE(ACPI, 0*32+22) /*A ACPI via MSR */
115 XEN_CPUFEATURE(MMX, 0*32+23) /*A Multimedia Extensions */
116 XEN_CPUFEATURE(FXSR, 0*32+24) /*A FXSAVE and FXRSTOR instructions */
117 XEN_CPUFEATURE(SSE, 0*32+25) /*A Streaming SIMD Extensions */
118 XEN_CPUFEATURE(SSE2, 0*32+26) /*A Streaming SIMD Extensions-2 */
119 XEN_CPUFEATURE(SS, 0*32+27) /*A CPU self snoop */
120 XEN_CPUFEATURE(HTT, 0*32+28) /*!A Hyper-Threading Technology */
121 XEN_CPUFEATURE(TM1, 0*32+29) /* Thermal Monitor 1 */
122 XEN_CPUFEATURE(PBE, 0*32+31) /* Pending Break Enable */
124 /* Intel-defined CPU features, CPUID level 0x00000001.ecx, word 1 */
125 XEN_CPUFEATURE(SSE3, 1*32+ 0) /*A Streaming SIMD Extensions-3 */
126 XEN_CPUFEATURE(PCLMULQDQ, 1*32+ 1) /*A Carry-less multiplication */
127 XEN_CPUFEATURE(DTES64, 1*32+ 2) /* 64-bit Debug Store */
128 XEN_CPUFEATURE(MONITOR, 1*32+ 3) /* Monitor/Mwait support */
129 XEN_CPUFEATURE(DSCPL, 1*32+ 4) /* CPL Qualified Debug Store */
130 XEN_CPUFEATURE(VMX, 1*32+ 5) /*h Virtual Machine Extensions */
131 XEN_CPUFEATURE(SMX, 1*32+ 6) /* Safer Mode Extensions */
132 XEN_CPUFEATURE(EIST, 1*32+ 7) /* Enhanced SpeedStep */
133 XEN_CPUFEATURE(TM2, 1*32+ 8) /* Thermal Monitor 2 */
134 XEN_CPUFEATURE(SSSE3, 1*32+ 9) /*A Supplemental Streaming SIMD Extensions-3 */
135 XEN_CPUFEATURE(FMA, 1*32+12) /*A Fused Multiply Add */
136 XEN_CPUFEATURE(CX16, 1*32+13) /*A CMPXCHG16B */
137 XEN_CPUFEATURE(XTPR, 1*32+14) /* Send Task Priority Messages */
138 XEN_CPUFEATURE(PDCM, 1*32+15) /* Perf/Debug Capability MSR */
139 XEN_CPUFEATURE(PCID, 1*32+17) /*H Process Context ID */
140 XEN_CPUFEATURE(DCA, 1*32+18) /* Direct Cache Access */
141 XEN_CPUFEATURE(SSE4_1, 1*32+19) /*A Streaming SIMD Extensions 4.1 */
142 XEN_CPUFEATURE(SSE4_2, 1*32+20) /*A Streaming SIMD Extensions 4.2 */
143 XEN_CPUFEATURE(X2APIC, 1*32+21) /*!A Extended xAPIC */
144 XEN_CPUFEATURE(MOVBE, 1*32+22) /*A movbe instruction */
145 XEN_CPUFEATURE(POPCNT, 1*32+23) /*A POPCNT instruction */
146 XEN_CPUFEATURE(TSC_DEADLINE, 1*32+24) /*S TSC Deadline Timer */
147 XEN_CPUFEATURE(AESNI, 1*32+25) /*A AES instructions */
148 XEN_CPUFEATURE(XSAVE, 1*32+26) /*A XSAVE/XRSTOR/XSETBV/XGETBV */
149 XEN_CPUFEATURE(OSXSAVE, 1*32+27) /*! OSXSAVE */
150 XEN_CPUFEATURE(AVX, 1*32+28) /*A Advanced Vector Extensions */
151 XEN_CPUFEATURE(F16C, 1*32+29) /*A Half-precision convert instruction */
152 XEN_CPUFEATURE(RDRAND, 1*32+30) /*!A Digital Random Number Generator */
153 XEN_CPUFEATURE(HYPERVISOR, 1*32+31) /*!A Running under some hypervisor */
155 /* AMD-defined CPU features, CPUID level 0x80000001.edx, word 2 */
156 XEN_CPUFEATURE(SYSCALL, 2*32+11) /*A SYSCALL/SYSRET */
157 XEN_CPUFEATURE(NX, 2*32+20) /*A Execute Disable */
158 XEN_CPUFEATURE(MMXEXT, 2*32+22) /*A AMD MMX extensions */
159 XEN_CPUFEATURE(FFXSR, 2*32+25) /*A FFXSR instruction optimizations */
160 XEN_CPUFEATURE(PAGE1GB, 2*32+26) /*H 1Gb large page support */
161 XEN_CPUFEATURE(RDTSCP, 2*32+27) /*A RDTSCP */
162 XEN_CPUFEATURE(LM, 2*32+29) /*A Long Mode (x86-64) */
163 XEN_CPUFEATURE(3DNOWEXT, 2*32+30) /*A AMD 3DNow! extensions */
164 XEN_CPUFEATURE(3DNOW, 2*32+31) /*A 3DNow! */
166 /* AMD-defined CPU features, CPUID level 0x80000001.ecx, word 3 */
167 XEN_CPUFEATURE(LAHF_LM, 3*32+ 0) /*A LAHF/SAHF in long mode */
168 XEN_CPUFEATURE(CMP_LEGACY, 3*32+ 1) /*!A If yes HyperThreading not valid */
169 XEN_CPUFEATURE(SVM, 3*32+ 2) /*h Secure virtual machine */
170 XEN_CPUFEATURE(EXTAPIC, 3*32+ 3) /* Extended APIC space */
171 XEN_CPUFEATURE(CR8_LEGACY, 3*32+ 4) /*S CR8 in 32-bit mode */
172 XEN_CPUFEATURE(ABM, 3*32+ 5) /*A Advanced bit manipulation */
173 XEN_CPUFEATURE(SSE4A, 3*32+ 6) /*A SSE-4A */
174 XEN_CPUFEATURE(MISALIGNSSE, 3*32+ 7) /*A Misaligned SSE mode */
175 XEN_CPUFEATURE(3DNOWPREFETCH, 3*32+ 8) /*A 3DNow prefetch instructions */
176 XEN_CPUFEATURE(OSVW, 3*32+ 9) /* OS Visible Workaround */
177 XEN_CPUFEATURE(IBS, 3*32+10) /* Instruction Based Sampling */
178 XEN_CPUFEATURE(XOP, 3*32+11) /*A extended AVX instructions */
179 XEN_CPUFEATURE(SKINIT, 3*32+12) /* SKINIT/STGI instructions */
180 XEN_CPUFEATURE(WDT, 3*32+13) /* Watchdog timer */
181 XEN_CPUFEATURE(LWP, 3*32+15) /* Light Weight Profiling */
182 XEN_CPUFEATURE(FMA4, 3*32+16) /*A 4 operands MAC instructions */
183 XEN_CPUFEATURE(NODEID_MSR, 3*32+19) /* NodeId MSR */
184 XEN_CPUFEATURE(TBM, 3*32+21) /*A trailing bit manipulations */
185 XEN_CPUFEATURE(TOPOEXT, 3*32+22) /* topology extensions CPUID leafs */
186 XEN_CPUFEATURE(DBEXT, 3*32+26) /*A data breakpoint extension */
187 XEN_CPUFEATURE(MONITORX, 3*32+29) /* MONITOR extension (MONITORX/MWAITX) */
189 /* Intel-defined CPU features, CPUID level 0x0000000D:1.eax, word 4 */
190 XEN_CPUFEATURE(XSAVEOPT, 4*32+ 0) /*A XSAVEOPT instruction */
191 XEN_CPUFEATURE(XSAVEC, 4*32+ 1) /*A XSAVEC/XRSTORC instructions */
192 XEN_CPUFEATURE(XGETBV1, 4*32+ 2) /*A XGETBV with %ecx=1 */
193 XEN_CPUFEATURE(XSAVES, 4*32+ 3) /*S XSAVES/XRSTORS instructions */
195 /* Intel-defined CPU features, CPUID level 0x00000007:0.ebx, word 5 */
196 XEN_CPUFEATURE(FSGSBASE, 5*32+ 0) /*A {RD,WR}{FS,GS}BASE instructions */
197 XEN_CPUFEATURE(TSC_ADJUST, 5*32+ 1) /*S TSC_ADJUST MSR available */
198 XEN_CPUFEATURE(SGX, 5*32+ 2) /* Software Guard extensions */
199 XEN_CPUFEATURE(BMI1, 5*32+ 3) /*A 1st bit manipulation extensions */
200 XEN_CPUFEATURE(HLE, 5*32+ 4) /*!a Hardware Lock Elision */
201 XEN_CPUFEATURE(AVX2, 5*32+ 5) /*A AVX2 instructions */
202 XEN_CPUFEATURE(FDP_EXCP_ONLY, 5*32+ 6) /*! x87 FDP only updated on exception. */
203 XEN_CPUFEATURE(SMEP, 5*32+ 7) /*S Supervisor Mode Execution Protection */
204 XEN_CPUFEATURE(BMI2, 5*32+ 8) /*A 2nd bit manipulation extensions */
205 XEN_CPUFEATURE(ERMS, 5*32+ 9) /*A Enhanced REP MOVSB/STOSB */
206 XEN_CPUFEATURE(INVPCID, 5*32+10) /*H Invalidate Process Context ID */
207 XEN_CPUFEATURE(RTM, 5*32+11) /*!A Restricted Transactional Memory */
208 XEN_CPUFEATURE(PQM, 5*32+12) /* Platform QoS Monitoring */
209 XEN_CPUFEATURE(NO_FPU_SEL, 5*32+13) /*! FPU CS/DS stored as zero */
210 XEN_CPUFEATURE(MPX, 5*32+14) /*s Memory Protection Extensions */
211 XEN_CPUFEATURE(PQE, 5*32+15) /* Platform QoS Enforcement */
212 XEN_CPUFEATURE(AVX512F, 5*32+16) /*A AVX-512 Foundation Instructions */
213 XEN_CPUFEATURE(AVX512DQ, 5*32+17) /*A AVX-512 Doubleword & Quadword Instrs */
214 XEN_CPUFEATURE(RDSEED, 5*32+18) /*A RDSEED instruction */
215 XEN_CPUFEATURE(ADX, 5*32+19) /*A ADCX, ADOX instructions */
216 XEN_CPUFEATURE(SMAP, 5*32+20) /*S Supervisor Mode Access Prevention */
217 XEN_CPUFEATURE(AVX512_IFMA, 5*32+21) /*A AVX-512 Integer Fused Multiply Add */
218 XEN_CPUFEATURE(CLFLUSHOPT, 5*32+23) /*A CLFLUSHOPT instruction */
219 XEN_CPUFEATURE(CLWB, 5*32+24) /*A CLWB instruction */
220 XEN_CPUFEATURE(PROC_TRACE, 5*32+25) /* Processor Trace */
221 XEN_CPUFEATURE(AVX512PF, 5*32+26) /*A AVX-512 Prefetch Instructions */
222 XEN_CPUFEATURE(AVX512ER, 5*32+27) /*A AVX-512 Exponent & Reciprocal Instrs */
223 XEN_CPUFEATURE(AVX512CD, 5*32+28) /*A AVX-512 Conflict Detection Instrs */
224 XEN_CPUFEATURE(SHA, 5*32+29) /*A SHA1 & SHA256 instructions */
225 XEN_CPUFEATURE(AVX512BW, 5*32+30) /*A AVX-512 Byte and Word Instructions */
226 XEN_CPUFEATURE(AVX512VL, 5*32+31) /*A AVX-512 Vector Length Extensions */
228 /* Intel-defined CPU features, CPUID level 0x00000007:0.ecx, word 6 */
229 XEN_CPUFEATURE(PREFETCHWT1, 6*32+ 0) /*A PREFETCHWT1 instruction */
230 XEN_CPUFEATURE(AVX512_VBMI, 6*32+ 1) /*A AVX-512 Vector Byte Manipulation Instrs */
231 XEN_CPUFEATURE(UMIP, 6*32+ 2) /*S User Mode Instruction Prevention */
232 XEN_CPUFEATURE(PKU, 6*32+ 3) /*H Protection Keys for Userspace */
233 XEN_CPUFEATURE(OSPKE, 6*32+ 4) /*! OS Protection Keys Enable */
234 XEN_CPUFEATURE(AVX512_VBMI2, 6*32+ 6) /*A Additional AVX-512 Vector Byte Manipulation Instrs */
235 XEN_CPUFEATURE(CET_SS, 6*32+ 7) /* CET - Shadow Stacks */
236 XEN_CPUFEATURE(GFNI, 6*32+ 8) /*A Galois Field Instrs */
237 XEN_CPUFEATURE(VAES, 6*32+ 9) /*A Vector AES Instrs */
238 XEN_CPUFEATURE(VPCLMULQDQ, 6*32+10) /*A Vector Carry-less Multiplication Instrs */
239 XEN_CPUFEATURE(AVX512_VNNI, 6*32+11) /*A Vector Neural Network Instrs */
240 XEN_CPUFEATURE(AVX512_BITALG, 6*32+12) /*A Support for VPOPCNT[B,W] and VPSHUFBITQMB */
241 XEN_CPUFEATURE(AVX512_VPOPCNTDQ, 6*32+14) /*A POPCNT for vectors of DW/QW */
242 XEN_CPUFEATURE(TSXLDTRK, 6*32+16) /*a TSX load tracking suspend/resume insns */
243 XEN_CPUFEATURE(RDPID, 6*32+22) /*A RDPID instruction */
244 XEN_CPUFEATURE(CLDEMOTE, 6*32+25) /*A CLDEMOTE instruction */
245 XEN_CPUFEATURE(MOVDIRI, 6*32+27) /*a MOVDIRI instruction */
246 XEN_CPUFEATURE(MOVDIR64B, 6*32+28) /*a MOVDIR64B instruction */
247 XEN_CPUFEATURE(ENQCMD, 6*32+29) /* ENQCMD{,S} instructions */
249 /* AMD-defined CPU features, CPUID level 0x80000007.edx, word 7 */
250 XEN_CPUFEATURE(ITSC, 7*32+ 8) /*a Invariant TSC */
251 XEN_CPUFEATURE(EFRO, 7*32+10) /* APERF/MPERF Read Only interface */
253 /* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */
254 XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */
255 XEN_CPUFEATURE(RSTR_FP_ERR_PTRS, 8*32+ 2) /*A (F)X{SAVE,RSTOR} always saves/restores FPU Error poi…
256 XEN_CPUFEATURE(WBNOINVD, 8*32+ 9) /* WBNOINVD instruction */
257 XEN_CPUFEATURE(IBPB, 8*32+12) /*A IBPB support only (no IBRS, used by AMD) */
258 XEN_CPUFEATURE(IBRS, 8*32+14) /* MSR_SPEC_CTRL.IBRS */
259 XEN_CPUFEATURE(AMD_STIBP, 8*32+15) /* MSR_SPEC_CTRL.STIBP */
260 XEN_CPUFEATURE(IBRS_ALWAYS, 8*32+16) /* IBRS preferred always on */
261 XEN_CPUFEATURE(STIBP_ALWAYS, 8*32+17) /* STIBP preferred always on */
262 XEN_CPUFEATURE(IBRS_FAST, 8*32+18) /* IBRS preferred over software options */
263 XEN_CPUFEATURE(IBRS_SAME_MODE, 8*32+19) /* IBRS provides same-mode protection */
264 XEN_CPUFEATURE(NO_LMSL, 8*32+20) /*S EFER.LMSLE no longer supported. */
265 XEN_CPUFEATURE(AMD_PPIN, 8*32+23) /* Protected Processor Inventory Number */
266 XEN_CPUFEATURE(AMD_SSBD, 8*32+24) /* MSR_SPEC_CTRL.SSBD available */
267 XEN_CPUFEATURE(VIRT_SSBD, 8*32+25) /* MSR_VIRT_SPEC_CTRL.SSBD */
268 XEN_CPUFEATURE(SSB_NO, 8*32+26) /* Hardware not vulnerable to SSB */
269 XEN_CPUFEATURE(PSFD, 8*32+28) /* MSR_SPEC_CTRL.PSFD */
271 /* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */
272 XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A AVX512 Neural Network Instructions */
273 XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A AVX512 Multiply Accumulation Single Precision */
274 XEN_CPUFEATURE(FSRM, 9*32+ 4) /*A Fast Short REP MOVS */
275 XEN_CPUFEATURE(AVX512_VP2INTERSECT, 9*32+8) /*a VP2INTERSECT{D,Q} insns */
276 XEN_CPUFEATURE(SRBDS_CTRL, 9*32+ 9) /* MSR_MCU_OPT_CTRL and RNGDS_MITG_DIS. */
277 XEN_CPUFEATURE(MD_CLEAR, 9*32+10) /*A VERW clears microarchitectural buffers */
278 XEN_CPUFEATURE(RTM_ALWAYS_ABORT, 9*32+11) /*! June 2021 TSX defeaturing in microcode. */
279 XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* MSR_TSX_FORCE_ABORT.RTM_ABORT */
280 XEN_CPUFEATURE(SERIALIZE, 9*32+14) /*a SERIALIZE insn */
281 XEN_CPUFEATURE(CET_IBT, 9*32+20) /* CET - Indirect Branch Tracking */
282 XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */
283 XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */
284 XEN_CPUFEATURE(L1D_FLUSH, 9*32+28) /*S MSR_FLUSH_CMD and L1D flush. */
285 XEN_CPUFEATURE(ARCH_CAPS, 9*32+29) /*a IA32_ARCH_CAPABILITIES MSR */
286 XEN_CPUFEATURE(CORE_CAPS, 9*32+30) /* IA32_CORE_CAPABILITIES MSR */
287 XEN_CPUFEATURE(SSBD, 9*32+31) /*A MSR_SPEC_CTRL.SSBD available */
289 /* Intel-defined CPU features, CPUID level 0x00000007:1.eax, word 10 */
290 XEN_CPUFEATURE(AVX_VNNI, 10*32+ 4) /*A AVX-VNNI Instructions */
291 XEN_CPUFEATURE(AVX512_BF16, 10*32+ 5) /*A AVX512 BFloat16 Instructions */
292 XEN_CPUFEATURE(FZRM, 10*32+10) /*A Fast Zero-length REP MOVSB */
293 XEN_CPUFEATURE(FSRS, 10*32+11) /*A Fast Short REP STOSB */
294 XEN_CPUFEATURE(FSRCS, 10*32+12) /*A Fast Short REP CMPSB/SCASB */
296 /* AMD-defined CPU features, CPUID level 0x80000021.eax, word 11 */
297 XEN_CPUFEATURE(LFENCE_DISPATCH, 11*32+ 2) /*A LFENCE always serializing */
298 XEN_CPUFEATURE(NSCB, 11*32+ 6) /*A Null Selector Clears Base (and limit too) */
313 * c-file-style: "BSD"
314 * c-basic-offset: 4
315 * tab-width: 4
316 * indent-tabs-mode: nil