Lines Matching +full:1 +full:- +full:512
1 // SPDX-License-Identifier: CDDL-1.0
10 * or https://opensource.org/licenses/CDDL-1.0.
76 * Given D+P drives in a group (including parity drives) and C-S physical
79 * of D+P and C-S as the number of groups; i.e. ngroups = LCM(D+P, C-S).
83 * which includes D=8 data and P=1 parity drive. There are 4 groups and
88 * data disks (8 data + 1 parity) spares (2)
90 * ^ | 2 | 6 | 1 | 11| 4 | 0 | 7 | 10| 8 | 9 | 13| 5 | 12| 3 | device map 0
92 * | | group 0 | group 1..| |
93 * | +-----------------------------------+-----------+-------|
94 * | | 0 1 2 3 4 5 6 7 8 | 36 37 38| | r
98 * s +-----------------------+-----------------------+-------+
99 * l | ..group 1 | group 2.. | |
100 * i +-----------------------+-----------------------+-------+
104 * | 66 67 68 69 70 71| 99 100 101 102 103 104| | 1
105 * | +-----------+-----------+-----------------------+-------+
107 * | +-----------+-----------+-----------------------+-------+
113 * | 9 | 11| 12| 2 | 4 | 1 | 3 | 0 | 10| 13| 8 | 5 | 6 | 7 | device map 1
116 * i +-----------------------+-----------+-----------+-------|
118 * e +-----------+-----------+-----------------------+-------+
119 * 1 |..group 6 | group 7 | | row 5
121 * | 3 | 5 | 10| 8 | 6 | 11| 12| 0 | 2 | 4 | 7 | 1 | 9 | 13| device map 2
124 * i +-----------------------------------------------+-------|
126 * e +-----------------------+-----------------------+-------+
128 * +-----------+-----------------------------------+-------+
133 * 1. The group count is not a relevant parameter when defining a dRAID
147 * In addition to the seed a checksum of the in-memory mapping is stored
158 * For dRAID the number of permutations has been limited to 512 to minimize
201 { 32, 512, 0xc6c87ba5b042650b, 0x000000f7eb08a156 }, /* 1.191 */
202 { 33, 512, 0xc3880d0c9d458304, 0x0000010734b5d160 }, /* 1.199 */
203 { 34, 512, 0xe920927e4d8b2c97, 0x00000118c1edbce0 }, /* 1.195 */
204 { 35, 512, 0x8da7fcda87bde316, 0x0000012a3e9f9110 }, /* 1.201 */
205 { 36, 512, 0xcf09937491514a29, 0x0000013bd6a24bef }, /* 1.194 */
206 { 37, 512, 0x9b5abbf345cbd7cc, 0x0000014b9d90fac3 }, /* 1.237 */
207 { 38, 512, 0x506312a44668d6a9, 0x0000015e1b5f6148 }, /* 1.242 */
208 { 39, 512, 0x71659ede62b4755f, 0x00000173ef029bcd }, /* 1.231 */
209 { 40, 512, 0xa7fde73fb74cf2d7, 0x000001866fb72748 }, /* 1.233 */
210 { 41, 512, 0x19e8b461a1dea1d3, 0x000001a046f76b23 }, /* 1.271 */
211 { 42, 512, 0x031c9b868cc3e976, 0x000001afa64c49d3 }, /* 1.263 */
212 { 43, 512, 0xbaa5125faa781854, 0x000001c76789e278 }, /* 1.270 */
213 { 44, 512, 0x4ed55052550d721b, 0x000001d800ccd8eb }, /* 1.281 */
214 { 45, 512, 0x0fd63ddbdff90677, 0x000001f08ad59ed2 }, /* 1.282 */
215 { 46, 512, 0x36d66546de7fdd6f, 0x000002016f09574b }, /* 1.286 */
216 { 47, 512, 0x99f997e7eafb69d7, 0x0000021e42e47cb6 }, /* 1.329 */
217 { 48, 512, 0xbecd9c2571312c5d, 0x000002320fe2872b }, /* 1.286 */
218 { 49, 512, 0xd97371329e488a32, 0x0000024cd73f2ca7 }, /* 1.322 */
219 { 50, 512, 0x30e9b136670749ee, 0x000002681c83b0e0 }, /* 1.335 */
220 { 51, 512, 0x11ad6bc8f47aaeb4, 0x0000027e9261b5d5 }, /* 1.305 */
221 { 52, 512, 0x68e445300af432c1, 0x0000029aa0eb7dbf }, /* 1.330 */
222 { 53, 512, 0x910fb561657ea98c, 0x000002b3dca04853 }, /* 1.365 */
223 { 54, 512, 0xd619693d8ce5e7a5, 0x000002cc280e9c97 }, /* 1.334 */
224 { 55, 512, 0x24e281f564dbb60a, 0x000002e9fa842713 }, /* 1.364 */
225 { 56, 512, 0x947a7d3bdaab44c5, 0x000003046680f72e }, /* 1.374 */
226 { 57, 512, 0x2d44fec9c093e0de, 0x00000324198ba810 }, /* 1.363 */
227 { 58, 512, 0x87743c272d29bb4c, 0x0000033ec48c9ac9 }, /* 1.401 */
228 { 59, 512, 0x96aa3b6f67f5d923, 0x0000034faead902c }, /* 1.392 */
229 { 60, 512, 0x94a4f1faf520b0d3, 0x0000037d713ab005 }, /* 1.360 */
230 { 61, 512, 0xb13ed3a272f711a2, 0x00000397368f3cbd }, /* 1.396 */
231 { 62, 512, 0x3b1b11805fa4a64a, 0x000003b8a5e2840c }, /* 1.453 */
232 { 63, 512, 0x4c74caad9172ba71, 0x000003d4be280290 }, /* 1.437 */
233 { 64, 512, 0x035ff643923dd29e, 0x000003fad6c355e1 }, /* 1.402 */
234 { 65, 512, 0x768e9171b11abd3c, 0x0000040eb07fed20 }, /* 1.459 */
235 { 66, 512, 0x75880e6f78a13ddd, 0x000004433d6acf14 }, /* 1.423 */
236 { 67, 512, 0x910b9714f698a877, 0x00000451ea65d5db }, /* 1.447 */
237 { 68, 512, 0x87f5db6f9fdcf5c7, 0x000004732169e3f7 }, /* 1.450 */
238 { 69, 512, 0x836d4968fbaa3706, 0x000004954068a380 }, /* 1.455 */
239 { 70, 512, 0xc567d73a036421ab, 0x000004bd7cb7bd3d }, /* 1.463 */
240 { 71, 512, 0x619df40f240b8fed, 0x000004e376c2e972 }, /* 1.463 */
241 { 72, 512, 0x42763a680d5bed8e, 0x000005084275c680 }, /* 1.452 */
242 { 73, 512, 0x5866f064b3230431, 0x0000052906f2c9ab }, /* 1.498 */
243 { 74, 512, 0x9fa08548b1621a44, 0x0000054708019247 }, /* 1.526 */
244 { 75, 512, 0xb6053078ce0fc303, 0x00000572cc5c72b0 }, /* 1.491 */
245 { 76, 512, 0x4a7aad7bf3890923, 0x0000058e987bc8e9 }, /* 1.470 */
246 { 77, 512, 0xe165613fd75b5a53, 0x000005c20473a211 }, /* 1.527 */
247 { 78, 512, 0x3ff154ac878163a6, 0x000005d659194bf3 }, /* 1.509 */
248 { 79, 512, 0x24b93ade0aa8a532, 0x0000060a201c4f8e }, /* 1.569 */
249 { 80, 512, 0xc18e2d14cd9bb554, 0x0000062c55cfe48c }, /* 1.555 */
250 { 81, 512, 0x98cc78302feb58b6, 0x0000066656a07194 }, /* 1.509 */
251 { 82, 512, 0xc6c5fd5a2abc0543, 0x0000067cff94fbf8 }, /* 1.596 */
252 { 83, 512, 0xa7962f514acbba21, 0x000006ab7b5afa2e }, /* 1.568 */
253 { 84, 512, 0xba02545069ddc6dc, 0x000006d19861364f }, /* 1.541 */
254 { 85, 512, 0x447c73192c35073e, 0x000006fce315ce35 }, /* 1.623 */
255 { 86, 512, 0x48beef9e2d42b0c2, 0x00000720a8e38b6b }, /* 1.620 */
256 { 87, 512, 0x4874cf98541a35e0, 0x00000758382a2273 }, /* 1.597 */
257 { 88, 512, 0xad4cf8333a31127a, 0x00000781e1651b1b }, /* 1.575 */
258 { 89, 512, 0x47ae4859d57888c1, 0x000007b27edbe5bc }, /* 1.627 */
259 { 90, 512, 0x06f7723cfe5d1891, 0x000007dc2a96d8eb }, /* 1.596 */
260 { 91, 512, 0xd4e44218d660576d, 0x0000080ac46f02d5 }, /* 1.622 */
261 { 92, 512, 0x7066702b0d5be1f2, 0x00000832c96d154e }, /* 1.695 */
262 { 93, 512, 0x011209b4f9e11fb9, 0x0000085eefda104c }, /* 1.605 */
263 { 94, 512, 0x47ffba30a0b35708, 0x00000899badc32dc }, /* 1.625 */
264 { 95, 512, 0x1a95a6ac4538aaa8, 0x000008b6b69a42b2 }, /* 1.687 */
265 { 96, 512, 0xbda2b239bb2008eb, 0x000008f22d2de38a }, /* 1.621 */
266 { 97, 512, 0x7ffa0bea90355c6c, 0x0000092e5b23b816 }, /* 1.699 */
267 { 98, 512, 0x1d56ba34be426795, 0x0000094f482e5d1b }, /* 1.688 */
268 { 99, 512, 0x0aa89d45c502e93d, 0x00000977d94a98ce }, /* 1.642 */
269 { 100, 512, 0x54369449f6857774, 0x000009c06c9b34cc }, /* 1.683 */
270 { 101, 512, 0xf7d4dd8445b46765, 0x000009e5dc542259 }, /* 1.755 */
271 { 102, 512, 0xfa8866312f169469, 0x00000a16b54eae93 }, /* 1.692 */
272 { 103, 512, 0xd8a5aea08aef3ff9, 0x00000a381d2cbfe7 }, /* 1.747 */
273 { 104, 512, 0x66bcd2c3d5f9ef0e, 0x00000a8191817be7 }, /* 1.751 */
274 { 105, 512, 0x3fb13a47a012ec81, 0x00000ab562b9a254 }, /* 1.751 */
275 { 106, 512, 0x43100f01c9e5e3ca, 0x00000aeee84c185f }, /* 1.726 */
276 { 107, 512, 0xca09c50ccee2d054, 0x00000b1c359c047d }, /* 1.788 */
277 { 108, 512, 0xd7176732ac503f9b, 0x00000b578bc52a73 }, /* 1.740 */
278 { 109, 512, 0xed206e51f8d9422d, 0x00000b8083e0d960 }, /* 1.780 */
279 { 110, 512, 0x17ead5dc6ba0dcd6, 0x00000bcfb1a32ca8 }, /* 1.836 */
280 { 111, 512, 0x5f1dc21e38a969eb, 0x00000c0171becdd6 }, /* 1.778 */
281 { 112, 512, 0xddaa973de33ec528, 0x00000c3edaba4b95 }, /* 1.831 */
282 { 113, 512, 0x2a5eccd7735a3630, 0x00000c630664e7df }, /* 1.825 */
283 { 114, 512, 0xafcccee5c0b71446, 0x00000cb65392f6e4 }, /* 1.826 */
284 { 115, 512, 0x8fa30c5e7b147e27, 0x00000cd4db391e55 }, /* 1.843 */
285 { 116, 512, 0x5afe0711fdfafd82, 0x00000d08cb4ec35d }, /* 1.826 */
286 { 117, 512, 0x533a6090238afd4c, 0x00000d336f115d1b }, /* 1.803 */
287 { 118, 512, 0x90cf11b595e39a84, 0x00000d8e041c2048 }, /* 1.857 */
288 { 119, 512, 0x0d61a3b809444009, 0x00000dcb798afe35 }, /* 1.877 */
289 { 120, 512, 0x7f34da0f54b0d114, 0x00000df3922664e1 }, /* 1.849 */
290 { 121, 512, 0xa52258d5b72f6551, 0x00000e4d37a9872d }, /* 1.867 */
291 { 122, 512, 0xc1de54d7672878db, 0x00000e6583a94cf6 }, /* 1.978 */
292 { 123, 512, 0x1d03354316a414ab, 0x00000ebffc50308d }, /* 1.947 */
293 { 124, 512, 0xcebdcc377665412c, 0x00000edee1997cea }, /* 1.865 */
294 { 125, 512, 0x4ddd4c04b1a12344, 0x00000f21d64b373f }, /* 1.881 */
295 { 126, 512, 0x64fc8f94e3973658, 0x00000f8f87a8896b }, /* 1.882 */
296 { 127, 512, 0x68765f78034a334e, 0x00000fb8fe62197e }, /* 1.867 */
297 { 128, 512, 0xaf36b871a303e816, 0x00000fec6f3afb1e }, /* 1.972 */
298 { 129, 512, 0x2a4cbf73866c3a28, 0x00001027febfe4e5 }, /* 1.896 */
299 { 130, 512, 0x9cb128aacdcd3b2f, 0x0000106aa8ac569d }, /* 1.965 */
300 { 131, 512, 0x5511d41c55869124, 0x000010bbd755ddf1 }, /* 1.963 */
301 { 132, 512, 0x42f92461937f284a, 0x000010fb8bceb3b5 }, /* 1.925 */
302 { 133, 512, 0xe2d89a1cf6f1f287, 0x0000114cf5331e34 }, /* 1.862 */
303 { 134, 512, 0xdc631a038956200e, 0x0000116428d2adc5 }, /* 2.042 */
304 { 135, 512, 0xb2e5ac222cd236be, 0x000011ca88e4d4d2 }, /* 1.935 */
305 { 136, 512, 0xbc7d8236655d88e7, 0x000011e39cb94e66 }, /* 2.005 */
306 { 137, 512, 0x073e02d88d2d8e75, 0x0000123136c7933c }, /* 2.041 */
307 { 138, 512, 0x3ddb9c3873166be0, 0x00001280e4ec6d52 }, /* 1.997 */
308 { 139, 512, 0x7d3b1a845420e1b5, 0x000012c2e7cd6a44 }, /* 1.996 */
309 { 140, 512, 0x60102308aa7b2a6c, 0x000012fc490e6c7d }, /* 2.053 */
310 { 141, 512, 0xdb22bb2f9eb894aa, 0x00001343f5a85a1a }, /* 1.971 */
311 { 142, 512, 0xd853f879a13b1606, 0x000013bb7d5f9048 }, /* 2.018 */
312 { 143, 512, 0x001620a03f804b1d, 0x000013e74cc794fd }, /* 1.961 */
313 { 144, 512, 0xfdb52dda76fbf667, 0x00001442d2f22480 }, /* 2.046 */
314 { 145, 512, 0xa9160110f66e24ff, 0x0000144b899f9dbb }, /* 1.968 */
315 { 146, 512, 0x77306a30379ae03b, 0x000014cb98eb1f81 }, /* 2.143 */
316 { 147, 512, 0x14f5985d2752319d, 0x000014feab821fc9 }, /* 2.064 */
317 { 148, 512, 0xa4b8ff11de7863f8, 0x0000154a0e60b9c9 }, /* 2.023 */
318 { 149, 512, 0x44b345426455c1b3, 0x000015999c3c569c }, /* 2.136 */
319 { 150, 512, 0x272677826049b46c, 0x000015c9697f4b92 }, /* 2.063 */
320 { 151, 512, 0x2f9216e2cd74fe40, 0x0000162b1f7bbd39 }, /* 1.974 */
321 { 152, 512, 0x706ae3e763ad8771, 0x00001661371c55e1 }, /* 2.210 */
322 { 153, 512, 0xf7fd345307c2480e, 0x000016e251f28b6a }, /* 2.006 */
323 { 154, 512, 0x6e94e3d26b3139eb, 0x000016f2429bb8c6 }, /* 2.193 */
324 { 155, 512, 0x5458bbfbb781fcba, 0x0000173efdeca1b9 }, /* 2.163 */
325 { 156, 512, 0xa80e2afeccd93b33, 0x000017bfdcb78adc }, /* 2.046 */
326 { 157, 512, 0x1e4ccbb22796cf9d, 0x00001826fdcc39c9 }, /* 2.084 */
327 { 158, 512, 0x8fba4b676aaa3663, 0x00001841a1379480 }, /* 2.264 */
328 { 159, 512, 0xf82b843814b315fa, 0x000018886e19b8a3 }, /* 2.074 */
329 { 160, 512, 0x7f21e920ecf753a3, 0x0000191812ca0ea7 }, /* 2.282 */
330 { 161, 512, 0x48bb8ea2c4caa620, 0x0000192f310faccf }, /* 2.148 */
331 { 162, 512, 0x5cdb652b4952c91b, 0x0000199e1d7437c7 }, /* 2.355 */
332 { 163, 512, 0x6ac1ba6f78c06cd4, 0x000019cd11f82c70 }, /* 2.164 */
333 { 164, 512, 0x9faf5f9ca2669a56, 0x00001a18d5431f6a }, /* 2.393 */
334 { 165, 512, 0xaa57e9383eb01194, 0x00001a9e7d253d85 }, /* 2.178 */
335 { 166, 512, 0x896967bf495c34d2, 0x00001afb8319b9fc }, /* 2.334 */
336 { 167, 512, 0xdfad5f05de225f1b, 0x00001b3a59c3093b }, /* 2.266 */
337 { 168, 512, 0xfd299a99f9f2abdd, 0x00001bb6f1a10799 }, /* 2.304 */
338 { 169, 512, 0xdda239e798fe9fd4, 0x00001bfae0c9692d }, /* 2.218 */
339 { 170, 512, 0x5fca670414a32c3e, 0x00001c22129dbcff }, /* 2.377 */
340 { 171, 512, 0x1bb8934314b087de, 0x00001c955db36cd0 }, /* 2.155 */
341 { 172, 512, 0xd96394b4b082200d, 0x00001cfc8619b7e6 }, /* 2.404 */
342 { 173, 512, 0xb612a7735b1c8cbc, 0x00001d303acdd585 }, /* 2.205 */
343 { 174, 512, 0x28e7430fe5875fe1, 0x00001d7ed5b3697d }, /* 2.359 */
344 { 175, 512, 0x5038e89efdd981b9, 0x00001dc40ec35c59 }, /* 2.158 */
345 { 176, 512, 0x075fd78f1d14db7c, 0x00001e31c83b4a2b }, /* 2.614 */
346 { 177, 512, 0xc50fafdb5021be15, 0x00001e7cdac82fbc }, /* 2.239 */
347 { 178, 512, 0xe6dc7572ce7b91c7, 0x00001edd8bb454fc }, /* 2.493 */
348 { 179, 512, 0x21f7843e7beda537, 0x00001f3a8e019d6c }, /* 2.327 */
349 { 180, 512, 0xc83385e20b43ec82, 0x00001f70735ec137 }, /* 2.231 */
350 { 181, 512, 0xca818217dddb21fd, 0x0000201ca44c5a3c }, /* 2.237 */
351 { 182, 512, 0xe6035defea48f933, 0x00002038e3346658 }, /* 2.691 */
352 { 183, 512, 0x47262a4f953dac5a, 0x000020c2e554314e }, /* 2.170 */
353 { 184, 512, 0xe24c7246260873ea, 0x000021197e618d64 }, /* 2.600 */
354 { 185, 512, 0xeef6b57c9b58e9e1, 0x0000217ea48ecddc }, /* 2.391 */
355 { 186, 512, 0x2becd3346e386142, 0x000021c496d4a5f9 }, /* 2.677 */
356 { 187, 512, 0x63c6207bdf3b40a3, 0x0000220e0f2eec0c }, /* 2.410 */
357 { 188, 512, 0x3056ce8989767d4b, 0x0000228eb76cd137 }, /* 2.776 */
358 { 189, 512, 0x91af61c307cee780, 0x000022e17e2ea501 }, /* 2.266 */
359 { 190, 512, 0xda359da225f6d54f, 0x00002358a2debc19 }, /* 2.717 */
360 { 191, 512, 0x0a5f7a2a55607ba0, 0x0000238a79dac18c }, /* 2.474 */
361 { 192, 512, 0x27bb75bf5224638a, 0x00002403a58e2351 }, /* 2.673 */
362 { 193, 512, 0x1ebfdb94630f5d0f, 0x00002492a10cb339 }, /* 2.420 */
363 { 194, 512, 0x6eae5e51d9c5f6fb, 0x000024ce4bf98715 }, /* 2.898 */
364 { 195, 512, 0x08d903b4daedc2e0, 0x0000250d1e15886c }, /* 2.363 */
365 { 196, 512, 0xc722a2f7fa7cd686, 0x0000258a99ed0c9e }, /* 2.747 */
366 { 197, 512, 0x8f71faf0e54e361d, 0x000025dee11976f5 }, /* 2.531 */
367 { 198, 512, 0x87f64695c91a54e7, 0x0000264e00a43da0 }, /* 2.707 */
368 { 199, 512, 0xc719cbac2c336b92, 0x000026d327277ac1 }, /* 2.315 */
369 { 200, 512, 0xe7e647afaf771ade, 0x000027523a5c44bf }, /* 3.012 */
370 { 201, 512, 0x12d4b5c38ce8c946, 0x0000273898432545 }, /* 2.378 */
371 { 202, 512, 0xf2e0cd4067bdc94a, 0x000027e47bb2c935 }, /* 2.969 */
372 { 203, 512, 0x21b79f14d6d947d3, 0x0000281e64977f0d }, /* 2.594 */
373 { 204, 512, 0x515093f952f18cd6, 0x0000289691a473fd }, /* 2.763 */
374 { 205, 512, 0xd47b160a1b1022c8, 0x00002903e8b52411 }, /* 2.457 */
375 { 206, 512, 0xc02fc96684715a16, 0x0000297515608601 }, /* 3.057 */
376 { 207, 512, 0xef51e68efba72ed0, 0x000029ef73604804 }, /* 2.590 */
377 { 208, 512, 0x9e3be6e5448b4f33, 0x00002a2846ed074b }, /* 3.047 */
378 { 209, 512, 0x81d446c6d5fec063, 0x00002a92ca693455 }, /* 2.676 */
379 { 210, 512, 0xff215de8224e57d5, 0x00002b2271fe3729 }, /* 2.993 */
380 { 211, 512, 0xe2524d9ba8f69796, 0x00002b64b99c3ba2 }, /* 2.457 */
381 { 212, 512, 0xf6b28e26097b7e4b, 0x00002bd768b6e068 }, /* 3.182 */
382 { 213, 512, 0x893a487f30ce1644, 0x00002c67f722b4b2 }, /* 2.563 */
383 { 214, 512, 0x386566c3fc9871df, 0x00002cc1cf8b4037 }, /* 3.025 */
384 { 215, 512, 0x1e0ed78edf1f558a, 0x00002d3948d36c7f }, /* 2.730 */
385 { 216, 512, 0xe3bc20c31e61f113, 0x00002d6d6b12e025 }, /* 3.036 */
386 { 217, 512, 0xd6c3ad2e23021882, 0x00002deff7572241 }, /* 2.722 */
387 { 218, 512, 0xb4a9f95cf0f69c5a, 0x00002e67d537aa36 }, /* 3.356 */
388 { 219, 512, 0x6e98ed6f6c38e82f, 0x00002e9720626789 }, /* 2.697 */
389 { 220, 512, 0x2e01edba33fddac7, 0x00002f407c6b0198 }, /* 2.979 */
390 { 221, 512, 0x559d02e1f5f57ccc, 0x00002fb6a5ab4f24 }, /* 2.858 */
391 { 222, 512, 0xac18f5a916adcd8e, 0x0000304ae1c5c57e }, /* 3.258 */
392 { 223, 512, 0x15789fbaddb86f4b, 0x0000306f6e019c78 }, /* 2.693 */
393 { 224, 512, 0xf4a9c36d5bc4c408, 0x000030da40434213 }, /* 3.259 */
394 { 225, 512, 0xf640f90fd2727f44, 0x00003189ed37b90c }, /* 2.733 */
395 { 226, 512, 0xb5313d390d61884a, 0x000031e152616b37 }, /* 3.235 */
396 { 227, 512, 0x4bae6b3ce9160939, 0x0000321f40aeac42 }, /* 2.983 */
397 { 228, 512, 0x838c34480f1a66a1, 0x000032f389c0f78e }, /* 3.308 */
398 { 229, 512, 0xb1c4a52c8e3d6060, 0x0000330062a40284 }, /* 2.715 */
399 { 230, 512, 0xe0f1110c6d0ed822, 0x0000338be435644f }, /* 3.540 */
400 { 231, 512, 0x9f1a8ccdcea68d4b, 0x000034045a4e97e1 }, /* 2.779 */
401 { 232, 512, 0x3261ed62223f3099, 0x000034702cfc401c }, /* 3.084 */
402 { 233, 512, 0xf2191e2311022d65, 0x00003509dd19c9fc }, /* 2.987 */
403 { 234, 512, 0xf102a395c2033abc, 0x000035654dc96fae }, /* 3.341 */
404 { 235, 512, 0x11fe378f027906b6, 0x000035b5193b0264 }, /* 2.793 */
405 { 236, 512, 0xf777f2c026b337aa, 0x000036704f5d9297 }, /* 3.518 */
406 { 237, 512, 0x1b04e9c2ee143f32, 0x000036dfbb7af218 }, /* 2.962 */
407 { 238, 512, 0x2fcec95266f9352c, 0x00003785c8df24a9 }, /* 3.196 */
408 { 239, 512, 0xfe2b0e47e427dd85, 0x000037cbdf5da729 }, /* 2.914 */
409 { 240, 512, 0x72b49bf2225f6c6d, 0x0000382227c15855 }, /* 3.408 */
410 { 241, 512, 0x50486b43df7df9c7, 0x0000389b88be6453 }, /* 2.903 */
411 { 242, 512, 0x5192a3e53181c8ab, 0x000038ddf3d67263 }, /* 3.778 */
412 { 243, 512, 0xe9f5d8365296fd5e, 0x0000399f1c6c9e9c }, /* 3.026 */
413 { 244, 512, 0xc740263f0301efa8, 0x00003a147146512d }, /* 3.347 */
414 { 245, 512, 0x23cd0f2b5671e67d, 0x00003ab10bcc0d9d }, /* 3.212 */
415 { 246, 512, 0x002ccc7e5cd41390, 0x00003ad6cd14a6c0 }, /* 3.482 */
416 { 247, 512, 0x9aafb3c02544b31b, 0x00003b8cb8779fb0 }, /* 3.146 */
417 { 248, 512, 0x72ba07a78b121999, 0x00003c24142a5a3f }, /* 3.626 */
418 { 249, 512, 0x3d784aa58edfc7b4, 0x00003cd084817d99 }, /* 2.952 */
419 { 250, 512, 0xaab750424d8004af, 0x00003d506a8e098e }, /* 3.463 */
420 { 251, 512, 0x84403fcf8e6b5ca2, 0x00003d4c54c2aec4 }, /* 3.131 */
421 { 252, 512, 0x71eb7455ec98e207, 0x00003e655715cf2c }, /* 3.538 */
422 { 253, 512, 0xd752b4f19301595b, 0x00003ecd7b2ca5ac }, /* 2.974 */
423 { 254, 512, 0xc4674129750499de, 0x00003e99e86d3e95 }, /* 3.843 */
424 { 255, 512, 0x9772baff5cd12ef5, 0x00003f895c019841 }, /* 3.088 */
471 * seed always generates the same mapping. We provide our own pseudo-random
477 VERIFY3U(map->dm_children, >=, VDEV_DRAID_MIN_CHILDREN); in vdev_draid_generate_perms()
478 VERIFY3U(map->dm_children, <=, VDEV_DRAID_MAX_CHILDREN); in vdev_draid_generate_perms()
479 VERIFY3U(map->dm_seed, !=, 0); in vdev_draid_generate_perms()
480 VERIFY3U(map->dm_nperms, !=, 0); in vdev_draid_generate_perms()
481 VERIFY0P(map->dm_perms); in vdev_draid_generate_perms()
486 * Only the tests/zfs-tests/cmd/draid/draid.c utility will provide in vdev_draid_generate_perms()
489 VERIFY3U(map->dm_checksum, !=, 0); in vdev_draid_generate_perms()
491 uint64_t children = map->dm_children; in vdev_draid_generate_perms()
492 uint64_t nperms = map->dm_nperms; in vdev_draid_generate_perms()
505 uint64_t draid_seed[2] = { VDEV_DRAID_SEED, map->dm_seed }; in vdev_draid_generate_perms()
509 * Perform a Fisher-Yates shuffle of each row using the previous in vdev_draid_generate_perms()
517 for (int j = children - 1; j > 0; j--) { in vdev_draid_generate_perms()
518 uint64_t k = vdev_draid_rand(draid_seed) % (j + 1); in vdev_draid_generate_perms()
529 int error = verify_perms(perms, children, nperms, map->dm_checksum); in vdev_draid_generate_perms()
563 uint64_t ncols = vdc->vdc_children; in vdev_draid_get_perm()
564 uint64_t poff = pindex % (vdc->vdc_nperms * ncols); in vdev_draid_get_perm()
566 *base = vdc->vdc_perms + (poff / ncols) * ncols; in vdev_draid_get_perm()
574 return ((base[index] + iter) % vdc->vdc_children); in vdev_draid_permute_id()
585 vdev_draid_config_t *vdc = vd->vdev_tsd; in vdev_draid_psize_to_asize()
586 uint64_t ashift = vd->vdev_ashift; in vdev_draid_psize_to_asize()
588 ASSERT3P(vd->vdev_ops, ==, &vdev_draid_ops); in vdev_draid_psize_to_asize()
590 uint64_t rows = ((psize - 1) / (vdc->vdc_ndata << ashift)) + 1; in vdev_draid_psize_to_asize()
591 uint64_t asize = (rows * vdc->vdc_groupwidth) << ashift; in vdev_draid_psize_to_asize()
594 ASSERT0(asize % (vdc->vdc_groupwidth)); in vdev_draid_psize_to_asize()
606 vdev_draid_config_t *vdc = vd->vdev_tsd; in vdev_draid_asize_to_psize()
608 ASSERT0(asize % vdc->vdc_groupwidth); in vdev_draid_asize_to_psize()
610 return ((asize / vdc->vdc_groupwidth) * vdc->vdc_ndata); in vdev_draid_asize_to_psize()
619 vdev_draid_config_t *vdc = vd->vdev_tsd; in vdev_draid_offset_to_group()
621 ASSERT3P(vd->vdev_ops, ==, &vdev_draid_ops); in vdev_draid_offset_to_group()
623 return (offset / vdc->vdc_groupsz); in vdev_draid_offset_to_group()
632 vdev_draid_config_t *vdc = vd->vdev_tsd; in vdev_draid_group_to_offset()
634 ASSERT3P(vd->vdev_ops, ==, &vdev_draid_ops); in vdev_draid_group_to_offset()
636 return (group * vdc->vdc_groupsz); in vdev_draid_group_to_offset()
650 * ABDs (e.g. rc->rc_size == parity_size).
655 uint64_t skip_size = 1ULL << zio->io_vd->vdev_top->vdev_ashift; in vdev_draid_map_alloc_write()
656 uint64_t parity_size = rr->rr_col[0].rc_size; in vdev_draid_map_alloc_write()
659 ASSERT3U(zio->io_type, ==, ZIO_TYPE_WRITE); in vdev_draid_map_alloc_write()
660 ASSERT3U(parity_size, ==, abd_get_size(rr->rr_col[0].rc_abd)); in vdev_draid_map_alloc_write()
662 for (uint64_t c = rr->rr_firstdatacol; c < rr->rr_cols; c++) { in vdev_draid_map_alloc_write()
663 raidz_col_t *rc = &rr->rr_col[c]; in vdev_draid_map_alloc_write()
665 if (rc->rc_size == 0) { in vdev_draid_map_alloc_write()
668 rc->rc_abd = abd_get_zeros(skip_size); in vdev_draid_map_alloc_write()
669 } else if (rc->rc_size == parity_size) { in vdev_draid_map_alloc_write()
671 rc->rc_abd = abd_get_offset_struct(&rc->rc_abdstruct, in vdev_draid_map_alloc_write()
672 zio->io_abd, abd_off, rc->rc_size); in vdev_draid_map_alloc_write()
675 ASSERT3U(rc->rc_size + skip_size, ==, parity_size); in vdev_draid_map_alloc_write()
676 rc->rc_abd = abd_alloc_gang(); in vdev_draid_map_alloc_write()
677 abd_gang_add(rc->rc_abd, abd_get_offset_size( in vdev_draid_map_alloc_write()
678 zio->io_abd, abd_off, rc->rc_size), B_TRUE); in vdev_draid_map_alloc_write()
679 abd_gang_add(rc->rc_abd, abd_get_zeros(skip_size), in vdev_draid_map_alloc_write()
683 ASSERT3U(abd_get_size(rc->rc_abd), ==, parity_size); in vdev_draid_map_alloc_write()
685 abd_off += rc->rc_size; in vdev_draid_map_alloc_write()
686 rc->rc_size = parity_size; in vdev_draid_map_alloc_write()
689 IMPLY(abd_offset != 0, abd_off == zio->io_size); in vdev_draid_map_alloc_write()
702 uint64_t skip_size = 1ULL << zio->io_vd->vdev_top->vdev_ashift; in vdev_draid_map_alloc_scrub()
703 uint64_t parity_size = rr->rr_col[0].rc_size; in vdev_draid_map_alloc_scrub()
707 ASSERT3U(zio->io_type, ==, ZIO_TYPE_READ); in vdev_draid_map_alloc_scrub()
708 ASSERT0P(rr->rr_abd_empty); in vdev_draid_map_alloc_scrub()
710 if (rr->rr_nempty > 0) { in vdev_draid_map_alloc_scrub()
711 rr->rr_abd_empty = abd_alloc_linear(rr->rr_nempty * skip_size, in vdev_draid_map_alloc_scrub()
715 for (uint64_t c = rr->rr_firstdatacol; c < rr->rr_cols; c++) { in vdev_draid_map_alloc_scrub()
716 raidz_col_t *rc = &rr->rr_col[c]; in vdev_draid_map_alloc_scrub()
718 if (rc->rc_size == 0) { in vdev_draid_map_alloc_scrub()
721 ASSERT3U(rr->rr_nempty, !=, 0); in vdev_draid_map_alloc_scrub()
722 rc->rc_abd = abd_get_offset_size(rr->rr_abd_empty, in vdev_draid_map_alloc_scrub()
725 } else if (rc->rc_size == parity_size) { in vdev_draid_map_alloc_scrub()
727 rc->rc_abd = abd_get_offset_struct(&rc->rc_abdstruct, in vdev_draid_map_alloc_scrub()
728 zio->io_abd, abd_off, rc->rc_size); in vdev_draid_map_alloc_scrub()
731 ASSERT3U(rc->rc_size + skip_size, ==, parity_size); in vdev_draid_map_alloc_scrub()
732 ASSERT3U(rr->rr_nempty, !=, 0); in vdev_draid_map_alloc_scrub()
733 rc->rc_abd = abd_alloc_gang(); in vdev_draid_map_alloc_scrub()
734 abd_gang_add(rc->rc_abd, abd_get_offset_size( in vdev_draid_map_alloc_scrub()
735 zio->io_abd, abd_off, rc->rc_size), B_TRUE); in vdev_draid_map_alloc_scrub()
736 abd_gang_add(rc->rc_abd, abd_get_offset_size( in vdev_draid_map_alloc_scrub()
737 rr->rr_abd_empty, skip_off, skip_size), B_TRUE); in vdev_draid_map_alloc_scrub()
741 uint64_t abd_size = abd_get_size(rc->rc_abd); in vdev_draid_map_alloc_scrub()
742 ASSERT3U(abd_size, ==, abd_get_size(rr->rr_col[0].rc_abd)); in vdev_draid_map_alloc_scrub()
748 abd_off += rc->rc_size; in vdev_draid_map_alloc_scrub()
749 rc->rc_size = abd_size; in vdev_draid_map_alloc_scrub()
752 IMPLY(abd_offset != 0, abd_off == zio->io_size); in vdev_draid_map_alloc_scrub()
753 ASSERT3U(skip_off, ==, rr->rr_nempty * skip_size); in vdev_draid_map_alloc_scrub()
769 ASSERT3U(zio->io_type, ==, ZIO_TYPE_READ); in vdev_draid_map_alloc_read()
771 for (uint64_t c = rr->rr_firstdatacol; c < rr->rr_cols; c++) { in vdev_draid_map_alloc_read()
772 raidz_col_t *rc = &rr->rr_col[c]; in vdev_draid_map_alloc_read()
774 if (rc->rc_size > 0) { in vdev_draid_map_alloc_read()
775 rc->rc_abd = abd_get_offset_struct(&rc->rc_abdstruct, in vdev_draid_map_alloc_read()
776 zio->io_abd, abd_off, rc->rc_size); in vdev_draid_map_alloc_read()
777 abd_off += rc->rc_size; in vdev_draid_map_alloc_read()
781 IMPLY(abd_offset != 0, abd_off == zio->io_size); in vdev_draid_map_alloc_read()
792 uint64_t skip_size = 1ULL << zio->io_vd->vdev_top->vdev_ashift; in vdev_draid_map_alloc_empty()
793 uint64_t parity_size = rr->rr_col[0].rc_size; in vdev_draid_map_alloc_empty()
796 ASSERT3U(zio->io_type, ==, ZIO_TYPE_READ); in vdev_draid_map_alloc_empty()
797 ASSERT0P(rr->rr_abd_empty); in vdev_draid_map_alloc_empty()
799 if (rr->rr_nempty > 0) { in vdev_draid_map_alloc_empty()
800 rr->rr_abd_empty = abd_alloc_linear(rr->rr_nempty * skip_size, in vdev_draid_map_alloc_empty()
804 for (uint64_t c = rr->rr_firstdatacol; c < rr->rr_cols; c++) { in vdev_draid_map_alloc_empty()
805 raidz_col_t *rc = &rr->rr_col[c]; in vdev_draid_map_alloc_empty()
807 if (rc->rc_size == 0) { in vdev_draid_map_alloc_empty()
810 ASSERT3U(rr->rr_nempty, !=, 0); in vdev_draid_map_alloc_empty()
811 ASSERT0P(rc->rc_abd); in vdev_draid_map_alloc_empty()
812 rc->rc_abd = abd_get_offset_size(rr->rr_abd_empty, in vdev_draid_map_alloc_empty()
815 } else if (rc->rc_size == parity_size) { in vdev_draid_map_alloc_empty()
817 ASSERT3P(rc->rc_abd, !=, NULL); in vdev_draid_map_alloc_empty()
821 * rc_tried to force the entire column to be re-read in vdev_draid_map_alloc_empty()
825 ASSERT3U(rc->rc_size + skip_size, ==, parity_size); in vdev_draid_map_alloc_empty()
826 ASSERT3U(rr->rr_nempty, !=, 0); in vdev_draid_map_alloc_empty()
827 ASSERT3P(rc->rc_abd, !=, NULL); in vdev_draid_map_alloc_empty()
828 ASSERT(!abd_is_gang(rc->rc_abd)); in vdev_draid_map_alloc_empty()
829 abd_t *read_abd = rc->rc_abd; in vdev_draid_map_alloc_empty()
830 rc->rc_abd = abd_alloc_gang(); in vdev_draid_map_alloc_empty()
831 abd_gang_add(rc->rc_abd, read_abd, B_TRUE); in vdev_draid_map_alloc_empty()
832 abd_gang_add(rc->rc_abd, abd_get_offset_size( in vdev_draid_map_alloc_empty()
833 rr->rr_abd_empty, skip_off, skip_size), B_TRUE); in vdev_draid_map_alloc_empty()
835 rc->rc_tried = 0; in vdev_draid_map_alloc_empty()
842 rc->rc_size = parity_size; in vdev_draid_map_alloc_empty()
845 ASSERT3U(skip_off, ==, rr->rr_nempty * skip_size); in vdev_draid_map_alloc_empty()
859 uint64_t skip_size = 1ULL << zio->io_vd->vdev_top->vdev_ashift; in vdev_draid_map_verify_empty()
860 uint64_t parity_size = rr->rr_col[0].rc_size; in vdev_draid_map_verify_empty()
861 uint64_t skip_off = parity_size - skip_size; in vdev_draid_map_verify_empty()
865 ASSERT3U(zio->io_type, ==, ZIO_TYPE_READ); in vdev_draid_map_verify_empty()
866 ASSERT3P(rr->rr_abd_empty, !=, NULL); in vdev_draid_map_verify_empty()
867 ASSERT3U(rr->rr_bigcols, >, 0); in vdev_draid_map_verify_empty()
871 for (int c = rr->rr_bigcols; c < rr->rr_cols; c++) { in vdev_draid_map_verify_empty()
872 raidz_col_t *rc = &rr->rr_col[c]; in vdev_draid_map_verify_empty()
874 ASSERT3P(rc->rc_abd, !=, NULL); in vdev_draid_map_verify_empty()
875 ASSERT3U(rc->rc_size, ==, parity_size); in vdev_draid_map_verify_empty()
877 if (abd_cmp_buf_off(rc->rc_abd, zero_buf, skip_off, in vdev_draid_map_verify_empty()
879 vdev_raidz_checksum_error(zio, rc, rc->rc_abd); in vdev_draid_map_verify_empty()
880 abd_zero_off(rc->rc_abd, skip_off, skip_size); in vdev_draid_map_verify_empty()
881 rc->rc_error = SET_ERROR(ECKSUM); in vdev_draid_map_verify_empty()
888 ASSERT3U(empty_off, ==, abd_get_size(rr->rr_abd_empty)); in vdev_draid_map_verify_empty()
904 vdev_draid_config_t *vdc = vd->vdev_tsd; in vdev_draid_logical_to_physical()
907 uint64_t ashift = vd->vdev_top->vdev_ashift; in vdev_draid_logical_to_physical()
926 uint64_t groupwidth = vdc->vdc_groupwidth; in vdev_draid_logical_to_physical()
927 uint64_t ngroups = vdc->vdc_ngroups; in vdev_draid_logical_to_physical()
928 uint64_t ndisks = vdc->vdc_ndisks; in vdev_draid_logical_to_physical()
934 uint64_t group = logical_offset / vdc->vdc_groupsz; in vdev_draid_logical_to_physical()
945 * - within a permutation there are ngroups groups spread over the in vdev_draid_logical_to_physical()
947 * - each permutation has (groupwidth * ngroups) / ndisks rows in vdev_draid_logical_to_physical()
948 * - so each permutation covers rows * slice portion of the disk in vdev_draid_logical_to_physical()
949 * - so we need to find the row where this IO group target begins in vdev_draid_logical_to_physical()
963 vdev_t *vd = zio->io_vd; in vdev_draid_map_alloc_row()
964 vdev_draid_config_t *vdc = vd->vdev_tsd; in vdev_draid_map_alloc_row()
965 uint64_t ashift = vd->vdev_top->vdev_ashift; in vdev_draid_map_alloc_row()
969 uint64_t start_offset = vdev_draid_group_to_offset(vd, group + 1); in vdev_draid_map_alloc_row()
977 start_offset - io_offset, 0); in vdev_draid_map_alloc_row()
986 IMPLY(abd_offset == 0 && io_size < zio->io_size, in vdev_draid_map_alloc_row()
987 (io_asize >> ashift) % vdc->vdc_groupwidth == 0); in vdev_draid_map_alloc_row()
1001 uint64_t ndisks = vdc->vdc_ndisks; in vdev_draid_map_alloc_row()
1002 uint64_t groupwidth = vdc->vdc_groupwidth; in vdev_draid_map_alloc_row()
1006 wrap = ndisks - groupstart; in vdev_draid_map_alloc_row()
1015 uint64_t q = psize / vdc->vdc_ndata; in vdev_draid_map_alloc_row()
1021 uint64_t r = psize - q * vdc->vdc_ndata; in vdev_draid_map_alloc_row()
1023 /* The number of "big columns" - those which contain remainder data. */ in vdev_draid_map_alloc_row()
1024 uint64_t bc = (r == 0 ? 0 : r + vdc->vdc_nparity); in vdev_draid_map_alloc_row()
1028 uint64_t tot = psize + (vdc->vdc_nparity * (q + (r == 0 ? 0 : 1))); in vdev_draid_map_alloc_row()
1030 ASSERT3U(vdc->vdc_nparity, >, 0); in vdev_draid_map_alloc_row()
1033 rr->rr_bigcols = bc; in vdev_draid_map_alloc_row()
1034 rr->rr_firstdatacol = vdc->vdc_nparity; in vdev_draid_map_alloc_row()
1036 rr->rr_offset = io_offset; in vdev_draid_map_alloc_row()
1037 rr->rr_size = io_size; in vdev_draid_map_alloc_row()
1045 raidz_col_t *rc = &rr->rr_col[i]; in vdev_draid_map_alloc_row()
1052 rc->rc_devidx = vdev_draid_permute_id(vdc, base, iter, c); in vdev_draid_map_alloc_row()
1053 rc->rc_offset = physical_offset; in vdev_draid_map_alloc_row()
1056 rc->rc_size = 0; in vdev_draid_map_alloc_row()
1058 rc->rc_size = (q + 1) << ashift; in vdev_draid_map_alloc_row()
1060 rc->rc_size = q << ashift; in vdev_draid_map_alloc_row()
1062 asize += rc->rc_size; in vdev_draid_map_alloc_row()
1066 rr->rr_nempty = roundup(tot, groupwidth) - tot; in vdev_draid_map_alloc_row()
1067 IMPLY(bc > 0, rr->rr_nempty == groupwidth - bc); in vdev_draid_map_alloc_row()
1070 for (uint64_t c = 0; c < rr->rr_firstdatacol; c++) { in vdev_draid_map_alloc_row()
1071 raidz_col_t *rc = &rr->rr_col[c]; in vdev_draid_map_alloc_row()
1072 rc->rc_abd = abd_alloc_linear(rc->rc_size, B_FALSE); in vdev_draid_map_alloc_row()
1080 if (zio->io_type == ZIO_TYPE_WRITE) { in vdev_draid_map_alloc_row()
1082 } else if ((rr->rr_nempty > 0) && in vdev_draid_map_alloc_row()
1083 (zio->io_flags & (ZIO_FLAG_SCRUB | ZIO_FLAG_RESILVER))) { in vdev_draid_map_alloc_row()
1086 ASSERT3U(zio->io_type, ==, ZIO_TYPE_READ); in vdev_draid_map_alloc_row()
1098 * - dRAID always allocates a full stripe width. Any extra sectors due
1103 * - When the block at the logical offset spans redundancy groups then two
1112 uint64_t abd_size = zio->io_size; in vdev_draid_map_alloc()
1113 uint64_t io_offset = zio->io_offset; in vdev_draid_map_alloc()
1115 int nrows = 1; in vdev_draid_map_alloc()
1120 vdev_t *vd = zio->io_vd; in vdev_draid_map_alloc()
1124 abd_size -= size; in vdev_draid_map_alloc()
1129 ASSERT3U(abd_offset, <, zio->io_size); in vdev_draid_map_alloc()
1132 size = vdev_draid_map_alloc_row(zio, &rr[1], in vdev_draid_map_alloc()
1139 rm->rm_ops = vdev_raidz_math_get_ops(); in vdev_draid_map_alloc()
1140 rm->rm_nrows = nrows; in vdev_draid_map_alloc()
1141 rm->rm_row[0] = rr[0]; in vdev_draid_map_alloc()
1143 rm->rm_row[1] = rr[1]; in vdev_draid_map_alloc()
1154 vdev_draid_config_t *vdc = vd->vdev_tsd; in vdev_draid_get_astart()
1156 ASSERT3P(vd->vdev_ops, ==, &vdev_draid_ops); in vdev_draid_get_astart()
1158 return (roundup(start, vdc->vdc_groupwidth << vd->vdev_ashift)); in vdev_draid_get_astart()
1162 * Allocatable space for dRAID is (children - nspares) * sizeof(smallest child)
1164 * 1 / (children - nspares) of its asize.
1169 vdev_draid_config_t *vdc = vd->vdev_tsd; in vdev_draid_min_asize()
1171 ASSERT3P(vd->vdev_ops, ==, &vdev_draid_ops); in vdev_draid_min_asize()
1174 (vd->vdev_min_asize + vdc->vdc_ndisks - 1) / (vdc->vdc_ndisks)); in vdev_draid_min_asize()
1184 vdev_draid_config_t *vdc = vd->vdev_tsd; in vdev_draid_min_alloc()
1186 ASSERT3P(vd->vdev_ops, ==, &vdev_draid_ops); in vdev_draid_min_alloc()
1188 return (vdc->vdc_ndata << vd->vdev_ashift); in vdev_draid_min_alloc()
1205 if (vd->vdev_ops == &vdev_spare_ops || in vdev_draid_missing()
1206 vd->vdev_ops == &vdev_replacing_ops) { in vdev_draid_missing()
1211 for (int c = 0; c < vd->vdev_children; c++) { in vdev_draid_missing()
1212 vdev_t *cvd = vd->vdev_child[c]; in vdev_draid_missing()
1225 if (vd->vdev_ops == &vdev_draid_spare_ops) { in vdev_draid_missing()
1231 if (vd->vdev_rebuild_txg != 0) in vdev_draid_missing()
1264 if (vd->vdev_ops == &vdev_spare_ops || in vdev_draid_partial()
1265 vd->vdev_ops == &vdev_replacing_ops) { in vdev_draid_partial()
1270 for (int c = 0; c < vd->vdev_children; c++) { in vdev_draid_partial()
1271 vdev_t *cvd = vd->vdev_child[c]; in vdev_draid_partial()
1283 if (vd->vdev_ops == &vdev_draid_spare_ops) { in vdev_draid_partial()
1289 if (vd->vdev_rebuild_txg != 0) in vdev_draid_partial()
1320 if (vd->vdev_ops == &vdev_draid_spare_ops) { in vdev_draid_readable()
1326 if (vd->vdev_ops == &vdev_spare_ops || in vdev_draid_readable()
1327 vd->vdev_ops == &vdev_replacing_ops) { in vdev_draid_readable()
1329 for (int c = 0; c < vd->vdev_children; c++) { in vdev_draid_readable()
1330 vdev_t *cvd = vd->vdev_child[c]; in vdev_draid_readable()
1351 if (vd->vdev_ops == &vdev_draid_spare_ops) in vdev_draid_find_spare()
1354 for (int c = 0; c < vd->vdev_children; c++) { in vdev_draid_find_spare()
1355 vdev_t *svd = vdev_draid_find_spare(vd->vdev_child[c]); in vdev_draid_find_spare()
1371 if (vd->vdev_ops == &vdev_draid_spare_ops) { in vdev_draid_faulted()
1380 vd = vd->vdev_parent; in vdev_draid_faulted()
1383 return (vd->vdev_ops == &vdev_replacing_ops || in vdev_draid_faulted()
1384 vd->vdev_ops == &vdev_spare_ops); in vdev_draid_faulted()
1394 vdev_draid_config_t *vdc = vd->vdev_tsd; in vdev_draid_group_degraded()
1396 ASSERT3P(vd->vdev_ops, ==, &vdev_draid_ops); in vdev_draid_group_degraded()
1407 for (uint64_t i = 0; i < vdc->vdc_groupwidth; i++) { in vdev_draid_group_degraded()
1408 uint64_t c = (groupstart + i) % vdc->vdc_ndisks; in vdev_draid_group_degraded()
1410 vdev_t *cvd = vd->vdev_child[cid]; in vdev_draid_group_degraded()
1434 vdev_draid_config_t *vdc = vd->vdev_tsd; in vdev_draid_group_missing()
1436 ASSERT3P(vd->vdev_ops, ==, &vdev_draid_ops); in vdev_draid_group_missing()
1447 for (uint64_t i = 0; i < vdc->vdc_groupwidth; i++) { in vdev_draid_group_missing()
1448 uint64_t c = (groupstart + i) % vdc->vdc_ndisks; in vdev_draid_group_missing()
1450 vdev_t *cvd = vd->vdev_child[cid]; in vdev_draid_group_missing()
1470 * is also based of the minimum child size in the top-level dRAID.
1479 ASSERT3P(vd->vdev_ops, ==, &vdev_draid_ops); in vdev_draid_calculate_asize()
1481 for (int c = 0; c < vd->vdev_children; c++) { in vdev_draid_calculate_asize()
1482 vdev_t *cvd = vd->vdev_child[c]; in vdev_draid_calculate_asize()
1484 if (cvd->vdev_ops == &vdev_draid_spare_ops) in vdev_draid_calculate_asize()
1487 asize = MIN(asize - 1, cvd->vdev_asize - 1) + 1; in vdev_draid_calculate_asize()
1488 max_asize = MIN(max_asize - 1, cvd->vdev_max_asize - 1) + 1; in vdev_draid_calculate_asize()
1489 logical_ashift = MAX(logical_ashift, cvd->vdev_ashift); in vdev_draid_calculate_asize()
1491 for (int c = 0; c < vd->vdev_children; c++) { in vdev_draid_calculate_asize()
1492 vdev_t *cvd = vd->vdev_child[c]; in vdev_draid_calculate_asize()
1494 if (cvd->vdev_ops == &vdev_draid_spare_ops) in vdev_draid_calculate_asize()
1497 physical_ashift, cvd->vdev_physical_ashift); in vdev_draid_calculate_asize()
1512 return (vd->vdev_ops == &vdev_draid_spare_ops || in vdev_draid_open_spares()
1513 vd->vdev_ops == &vdev_replacing_ops || in vdev_draid_open_spares()
1514 vd->vdev_ops == &vdev_spare_ops); in vdev_draid_open_spares()
1527 * Open a top-level dRAID vdev.
1533 vdev_draid_config_t *vdc = vd->vdev_tsd; in vdev_draid_open()
1534 uint64_t nparity = vdc->vdc_nparity; in vdev_draid_open()
1538 vd->vdev_children < nparity + 1) { in vdev_draid_open()
1539 vd->vdev_stat.vs_aux = VDEV_AUX_BAD_LABEL; in vdev_draid_open()
1552 for (int c = 0; c < vd->vdev_children; c++) { in vdev_draid_open()
1553 if (vd->vdev_child[c]->vdev_open_error != 0) { in vdev_draid_open()
1555 vd->vdev_stat.vs_aux = VDEV_AUX_NO_REPLICAS; in vdev_draid_open()
1581 child_asize = ((child_asize - VDEV_DRAID_REFLOW_RESERVE) / in vdev_draid_open()
1583 child_max_asize = ((child_max_asize - VDEV_DRAID_REFLOW_RESERVE) / in vdev_draid_open()
1586 *asize = (((child_asize * vdc->vdc_ndisks) / vdc->vdc_groupsz) * in vdev_draid_open()
1587 vdc->vdc_groupsz); in vdev_draid_open()
1588 *max_asize = (((child_max_asize * vdc->vdc_ndisks) / vdc->vdc_groupsz) * in vdev_draid_open()
1589 vdc->vdc_groupsz); in vdev_draid_open()
1595 * Close a top-level dRAID vdev.
1600 for (int c = 0; c < vd->vdev_children; c++) { in vdev_draid_close()
1601 if (vd->vdev_child[c] != NULL) in vdev_draid_close()
1602 vdev_close(vd->vdev_child[c]); in vdev_draid_close()
1610 * - Exceed the maximum allowed block size (SPA_MAXBLOCKSIZE), or
1611 * - Span dRAID redundancy groups.
1617 vdev_draid_config_t *vdc = vd->vdev_tsd; in vdev_draid_rebuild_asize()
1619 ASSERT3P(vd->vdev_ops, ==, &vdev_draid_ops); in vdev_draid_rebuild_asize()
1621 uint64_t ashift = vd->vdev_ashift; in vdev_draid_rebuild_asize()
1622 uint64_t ndata = vdc->vdc_ndata; in vdev_draid_rebuild_asize()
1623 uint64_t psize = MIN(P2ROUNDUP(max_segment * ndata, 1 << ashift), in vdev_draid_rebuild_asize()
1627 ASSERT0(asize % (vdc->vdc_groupwidth << ashift)); in vdev_draid_rebuild_asize()
1635 uint64_t left = vdev_draid_group_to_offset(vd, group + 1) - start; in vdev_draid_rebuild_asize()
1638 ASSERT0(chunk_size % (vdc->vdc_groupwidth << ashift)); in vdev_draid_rebuild_asize()
1640 vdev_draid_offset_to_group(vd, start + chunk_size - 1)); in vdev_draid_rebuild_asize()
1655 vdev_draid_config_t *vdc = vd->vdev_tsd; in vdev_draid_metaslab_init()
1657 ASSERT3P(vd->vdev_ops, ==, &vdev_draid_ops); in vdev_draid_metaslab_init()
1659 uint64_t sz = vdc->vdc_groupwidth << vd->vdev_ashift; in vdev_draid_metaslab_init()
1661 uint64_t asize = ((*ms_size - (astart - *ms_start)) / sz) * sz; in vdev_draid_metaslab_init()
1683 for (uint64_t i = 0; i < vd->vdev_children; i++) { in vdev_draid_spare_create()
1684 vdev_t *cvd = vd->vdev_child[i]; in vdev_draid_spare_create()
1686 if (cvd->vdev_ops == &vdev_draid_ops) { in vdev_draid_spare_create()
1687 vdev_draid_config_t *vdc = cvd->vdev_tsd; in vdev_draid_spare_create()
1688 draid_nspares += vdc->vdc_nspares; in vdev_draid_spare_create()
1713 for (uint64_t vdev_id = 0; vdev_id < vd->vdev_children; vdev_id++) { in vdev_draid_spare_create()
1714 vdev_t *cvd = vd->vdev_child[vdev_id]; in vdev_draid_spare_create()
1717 if (cvd->vdev_ops != &vdev_draid_ops) in vdev_draid_spare_create()
1720 vdev_draid_config_t *vdc = cvd->vdev_tsd; in vdev_draid_spare_create()
1721 uint64_t nspares = vdc->vdc_nspares; in vdev_draid_spare_create()
1722 uint64_t nparity = vdc->vdc_nparity; in vdev_draid_spare_create()
1726 (void) snprintf(path, sizeof (path) - 1, in vdev_draid_spare_create()
1727 "%s%llu-%llu-%llu", VDEV_TYPE_DRAID, in vdev_draid_spare_create()
1737 cvd->vdev_guid); in vdev_draid_spare_create()
1741 fnvlist_add_uint64(spare, ZPOOL_CONFIG_IS_SPARE, 1); in vdev_draid_spare_create()
1742 fnvlist_add_uint64(spare, ZPOOL_CONFIG_WHOLE_DISK, 1); in vdev_draid_spare_create()
1744 cvd->vdev_ashift); in vdev_draid_spare_create()
1784 vdev_draid_offset_to_group(vd, offset + asize - 1)); in vdev_draid_need_resilver()
1790 * as are blocks in non-degraded groups. in vdev_draid_need_resilver()
1792 if (!vdev_dtl_contains(vd, DTL_PARTIAL, phys_birth, 1)) in vdev_draid_need_resilver()
1795 if (vdev_draid_group_missing(vd, offset, phys_birth, 1)) in vdev_draid_need_resilver()
1800 vdev_draid_offset_to_group(vd, offset + asize - 1)) { in vdev_draid_need_resilver()
1802 offset + asize, phys_birth, 1)) in vdev_draid_need_resilver()
1813 if (vd->vdev_ops->vdev_op_leaf && vd->vdev_rebuild_txg) in vdev_draid_rebuilding()
1816 for (int i = 0; i < vd->vdev_children; i++) { in vdev_draid_rebuilding()
1817 if (vdev_draid_rebuilding(vd->vdev_child[i])) { in vdev_draid_rebuilding()
1830 logical_rs.rs_start = rr->rr_offset; in vdev_draid_io_verify()
1832 vdev_draid_psize_to_asize(vd, rr->rr_size, 0); in vdev_draid_io_verify()
1834 raidz_col_t *rc = &rr->rr_col[col]; in vdev_draid_io_verify()
1835 vdev_t *cvd = vd->vdev_child[rc->rc_devidx]; in vdev_draid_io_verify()
1839 ASSERT3U(rc->rc_offset, ==, physical_rs.rs_start); in vdev_draid_io_verify()
1840 ASSERT3U(rc->rc_offset, <, physical_rs.rs_end); in vdev_draid_io_verify()
1841 ASSERT3U(rc->rc_offset + rc->rc_size, ==, physical_rs.rs_end); in vdev_draid_io_verify()
1847 * 1. Generate the parity data
1855 vdev_t *vd = zio->io_vd; in vdev_draid_io_start_write()
1856 raidz_map_t *rm = zio->io_vsd; in vdev_draid_io_start_write()
1860 for (int c = 0; c < rr->rr_cols; c++) { in vdev_draid_io_start_write()
1861 raidz_col_t *rc = &rr->rr_col[c]; in vdev_draid_io_start_write()
1867 ASSERT3U(rc->rc_size, !=, 0); in vdev_draid_io_start_write()
1873 vd->vdev_child[rc->rc_devidx], rc->rc_offset, in vdev_draid_io_start_write()
1874 rc->rc_abd, rc->rc_size, zio->io_type, zio->io_priority, in vdev_draid_io_start_write()
1881 * 1. The vdev_draid_map_alloc() function will create a minimal raidz
1882 * mapping for the read based on the zio->io_flags. There are two
1883 * possible mappings either 1) a normal read, or 2) a scrub/resilver.
1890 vdev_t *vd = zio->io_vd; in vdev_draid_io_start_read()
1893 IMPLY(zio->io_priority == ZIO_PRIORITY_REBUILD, rr->rr_nempty == 0); in vdev_draid_io_start_read()
1899 * have been allocated to store them and rc->rc_size is increased. in vdev_draid_io_start_read()
1901 for (int c = rr->rr_cols - 1; c >= 0; c--) { in vdev_draid_io_start_read()
1902 raidz_col_t *rc = &rr->rr_col[c]; in vdev_draid_io_start_read()
1903 vdev_t *cvd = vd->vdev_child[rc->rc_devidx]; in vdev_draid_io_start_read()
1905 if (!vdev_draid_readable(cvd, rc->rc_offset)) { in vdev_draid_io_start_read()
1906 if (c >= rr->rr_firstdatacol) in vdev_draid_io_start_read()
1907 rr->rr_missingdata++; in vdev_draid_io_start_read()
1909 rr->rr_missingparity++; in vdev_draid_io_start_read()
1910 rc->rc_error = SET_ERROR(ENXIO); in vdev_draid_io_start_read()
1911 rc->rc_tried = 1; in vdev_draid_io_start_read()
1912 rc->rc_skipped = 1; in vdev_draid_io_start_read()
1916 if (vdev_draid_missing(cvd, rc->rc_offset, zio->io_txg, 1)) { in vdev_draid_io_start_read()
1917 if (c >= rr->rr_firstdatacol) in vdev_draid_io_start_read()
1918 rr->rr_missingdata++; in vdev_draid_io_start_read()
1920 rr->rr_missingparity++; in vdev_draid_io_start_read()
1921 rc->rc_error = SET_ERROR(ESTALE); in vdev_draid_io_start_read()
1922 rc->rc_skipped = 1; in vdev_draid_io_start_read()
1931 if (rc->rc_size == 0) { in vdev_draid_io_start_read()
1932 rc->rc_skipped = 1; in vdev_draid_io_start_read()
1936 if (zio->io_flags & ZIO_FLAG_RESILVER) { in vdev_draid_io_start_read()
1952 if (zio->io_priority == ZIO_PRIORITY_REBUILD) { in vdev_draid_io_start_read()
1954 if (c >= rr->rr_firstdatacol) in vdev_draid_io_start_read()
1955 rr->rr_missingdata++; in vdev_draid_io_start_read()
1957 rr->rr_missingparity++; in vdev_draid_io_start_read()
1958 rc->rc_error = SET_ERROR(ESTALE); in vdev_draid_io_start_read()
1959 rc->rc_skipped = 1; in vdev_draid_io_start_read()
1960 rc->rc_allow_repair = 1; in vdev_draid_io_start_read()
1963 rc->rc_allow_repair = 0; in vdev_draid_io_start_read()
1966 rc->rc_allow_repair = 1; in vdev_draid_io_start_read()
1979 rc->rc_offset); in vdev_draid_io_start_read()
1980 if (svd && (svd->vdev_ops == &vdev_spare_ops || in vdev_draid_io_start_read()
1981 svd->vdev_ops == &vdev_replacing_ops)) { in vdev_draid_io_start_read()
1982 rc->rc_force_repair = 1; in vdev_draid_io_start_read()
1985 rc->rc_allow_repair = 1; in vdev_draid_io_start_read()
1993 if ((cvd->vdev_ops == &vdev_spare_ops || in vdev_draid_io_start_read()
1994 cvd->vdev_ops == &vdev_replacing_ops) && in vdev_draid_io_start_read()
1996 rc->rc_force_repair = 1; in vdev_draid_io_start_read()
1997 rc->rc_allow_repair = 1; in vdev_draid_io_start_read()
2001 if (vdev_sit_out_reads(cvd, zio->io_flags)) { in vdev_draid_io_start_read()
2002 rr->rr_outlier_cnt++; in vdev_draid_io_start_read()
2003 ASSERT0(rc->rc_latency_outlier); in vdev_draid_io_start_read()
2004 rc->rc_latency_outlier = 1; in vdev_draid_io_start_read()
2013 if (rr->rr_outlier_cnt > 0 && in vdev_draid_io_start_read()
2014 (rr->rr_firstdatacol - rr->rr_missingparity) >= in vdev_draid_io_start_read()
2015 (rr->rr_missingdata + 1)) { in vdev_draid_io_start_read()
2017 for (int c = rr->rr_cols - 1; c >= rr->rr_firstdatacol; c--) { in vdev_draid_io_start_read()
2018 raidz_col_t *rc = &rr->rr_col[c]; in vdev_draid_io_start_read()
2020 if (rc->rc_error == 0 && rc->rc_latency_outlier) { in vdev_draid_io_start_read()
2021 rr->rr_missingdata++; in vdev_draid_io_start_read()
2022 rc->rc_error = SET_ERROR(EAGAIN); in vdev_draid_io_start_read()
2023 rc->rc_skipped = 1; in vdev_draid_io_start_read()
2035 if ((rr->rr_missingdata > 0 || rr->rr_missingparity > 0) && in vdev_draid_io_start_read()
2036 rr->rr_nempty > 0 && rr->rr_abd_empty == NULL) { in vdev_draid_io_start_read()
2040 for (int c = rr->rr_cols - 1; c >= 0; c--) { in vdev_draid_io_start_read()
2041 raidz_col_t *rc = &rr->rr_col[c]; in vdev_draid_io_start_read()
2042 vdev_t *cvd = vd->vdev_child[rc->rc_devidx]; in vdev_draid_io_start_read()
2044 if (rc->rc_error || rc->rc_size == 0) in vdev_draid_io_start_read()
2047 if (c >= rr->rr_firstdatacol || rr->rr_missingdata > 0 || in vdev_draid_io_start_read()
2048 (zio->io_flags & (ZIO_FLAG_SCRUB | ZIO_FLAG_RESILVER))) { in vdev_draid_io_start_read()
2050 rc->rc_offset, rc->rc_abd, rc->rc_size, in vdev_draid_io_start_read()
2051 zio->io_type, zio->io_priority, 0, in vdev_draid_io_start_read()
2063 vdev_t *vd __maybe_unused = zio->io_vd; in vdev_draid_io_start()
2065 ASSERT3P(vd->vdev_ops, ==, &vdev_draid_ops); in vdev_draid_io_start()
2066 ASSERT3U(zio->io_offset, ==, vdev_draid_get_astart(vd, zio->io_offset)); in vdev_draid_io_start()
2069 zio->io_vsd = rm; in vdev_draid_io_start()
2070 zio->io_vsd_ops = &vdev_raidz_vsd_ops; in vdev_draid_io_start()
2072 if (zio->io_type == ZIO_TYPE_WRITE) { in vdev_draid_io_start()
2073 for (int i = 0; i < rm->rm_nrows; i++) { in vdev_draid_io_start()
2074 vdev_draid_io_start_write(zio, rm->rm_row[i]); in vdev_draid_io_start()
2077 ASSERT(zio->io_type == ZIO_TYPE_READ); in vdev_draid_io_start()
2079 for (int i = 0; i < rm->rm_nrows; i++) { in vdev_draid_io_start()
2080 vdev_draid_io_start_read(zio, rm->rm_row[i]); in vdev_draid_io_start()
2100 vdev_draid_config_t *vdc = vd->vdev_tsd; in vdev_draid_state_change()
2101 ASSERT(vd->vdev_ops == &vdev_draid_ops); in vdev_draid_state_change()
2103 if (faulted > vdc->vdc_nparity) in vdev_draid_state_change()
2116 vdev_t *raidvd = cvd->vdev_parent; in vdev_draid_xlate()
2117 ASSERT(raidvd->vdev_ops == &vdev_draid_ops); in vdev_draid_xlate()
2119 vdev_draid_config_t *vdc = raidvd->vdev_tsd; in vdev_draid_xlate()
2120 uint64_t ashift = raidvd->vdev_top->vdev_ashift; in vdev_draid_xlate()
2122 /* Make sure the offsets are block-aligned */ in vdev_draid_xlate()
2123 ASSERT0(logical_rs->rs_start % (1 << ashift)); in vdev_draid_xlate()
2124 ASSERT0(logical_rs->rs_end % (1 << ashift)); in vdev_draid_xlate()
2126 uint64_t logical_start = logical_rs->rs_start; in vdev_draid_xlate()
2127 uint64_t logical_end = logical_rs->rs_end; in vdev_draid_xlate()
2136 physical_rs->rs_start = logical_start; in vdev_draid_xlate()
2137 physical_rs->rs_end = logical_start; in vdev_draid_xlate()
2138 remain_rs->rs_start = MIN(astart, logical_end); in vdev_draid_xlate()
2139 remain_rs->rs_end = logical_end; in vdev_draid_xlate()
2145 * to multiple non-contiguous physical ranges. This is handled by in vdev_draid_xlate()
2152 uint64_t nextstart = vdev_draid_group_to_offset(raidvd, group + 1); in vdev_draid_xlate()
2170 * (zero-length) physical range being returned. in vdev_draid_xlate()
2172 for (uint64_t i = 0; i < vdc->vdc_groupwidth; i++) { in vdev_draid_xlate()
2173 uint64_t c = (groupstart + i) % vdc->vdc_ndisks; in vdev_draid_xlate()
2182 if (id == cvd->vdev_id) { in vdev_draid_xlate()
2183 uint64_t b_size = (logical_end >> ashift) - in vdev_draid_xlate()
2186 end = start + ((((b_size - 1) / in vdev_draid_xlate()
2187 vdc->vdc_groupwidth) + 1) << ashift); in vdev_draid_xlate()
2191 physical_rs->rs_start = start; in vdev_draid_xlate()
2192 physical_rs->rs_end = end; in vdev_draid_xlate()
2195 * Only top-level vdevs are allowed to set remain_rs because in vdev_draid_xlate()
2199 remain_rs->rs_start = logical_end; in vdev_draid_xlate()
2200 remain_rs->rs_end = logical_rs->rs_end; in vdev_draid_xlate()
2202 ASSERT3U(physical_rs->rs_start, <=, logical_start); in vdev_draid_xlate()
2203 ASSERT3U(physical_rs->rs_end - physical_rs->rs_start, <=, in vdev_draid_xlate()
2204 logical_end - logical_start); in vdev_draid_xlate()
2213 ASSERT3P(vd->vdev_ops, ==, &vdev_draid_ops); in vdev_draid_config_generate()
2214 vdev_draid_config_t *vdc = vd->vdev_tsd; in vdev_draid_config_generate()
2216 fnvlist_add_uint64(nv, ZPOOL_CONFIG_NPARITY, vdc->vdc_nparity); in vdev_draid_config_generate()
2217 fnvlist_add_uint64(nv, ZPOOL_CONFIG_DRAID_NDATA, vdc->vdc_ndata); in vdev_draid_config_generate()
2218 fnvlist_add_uint64(nv, ZPOOL_CONFIG_DRAID_NSPARES, vdc->vdc_nspares); in vdev_draid_config_generate()
2219 fnvlist_add_uint64(nv, ZPOOL_CONFIG_DRAID_NGROUPS, vdc->vdc_ngroups); in vdev_draid_config_generate()
2249 nspares > 100 || nspares > (children - (ndata + nparity))) { in vdev_draid_init()
2277 vdc->vdc_ndata = ndata; in vdev_draid_init()
2278 vdc->vdc_nparity = nparity; in vdev_draid_init()
2279 vdc->vdc_nspares = nspares; in vdev_draid_init()
2280 vdc->vdc_children = children; in vdev_draid_init()
2281 vdc->vdc_ngroups = ngroups; in vdev_draid_init()
2282 vdc->vdc_nperms = map->dm_nperms; in vdev_draid_init()
2284 error = vdev_draid_generate_perms(map, &vdc->vdc_perms); in vdev_draid_init()
2293 vdc->vdc_groupwidth = vdc->vdc_ndata + vdc->vdc_nparity; in vdev_draid_init()
2294 vdc->vdc_ndisks = vdc->vdc_children - vdc->vdc_nspares; in vdev_draid_init()
2295 vdc->vdc_groupsz = vdc->vdc_groupwidth * VDEV_DRAID_ROWHEIGHT; in vdev_draid_init()
2296 vdc->vdc_devslicesz = (vdc->vdc_groupsz * vdc->vdc_ngroups) / in vdev_draid_init()
2297 vdc->vdc_ndisks; in vdev_draid_init()
2299 ASSERT3U(vdc->vdc_groupwidth, >=, 2); in vdev_draid_init()
2300 ASSERT3U(vdc->vdc_groupwidth, <=, vdc->vdc_ndisks); in vdev_draid_init()
2301 ASSERT3U(vdc->vdc_groupsz, >=, 2 * VDEV_DRAID_ROWHEIGHT); in vdev_draid_init()
2302 ASSERT3U(vdc->vdc_devslicesz, >=, VDEV_DRAID_ROWHEIGHT); in vdev_draid_init()
2303 ASSERT0(vdc->vdc_devslicesz % VDEV_DRAID_ROWHEIGHT); in vdev_draid_init()
2304 ASSERT3U((vdc->vdc_groupwidth * vdc->vdc_ngroups) % in vdev_draid_init()
2305 vdc->vdc_ndisks, ==, 0); in vdev_draid_init()
2315 vdev_draid_config_t *vdc = vd->vdev_tsd; in vdev_draid_fini()
2317 vmem_free(vdc->vdc_perms, sizeof (uint8_t) * in vdev_draid_fini()
2318 vdc->vdc_children * vdc->vdc_nperms); in vdev_draid_fini()
2325 vdev_draid_config_t *vdc = vd->vdev_tsd; in vdev_draid_nparity()
2327 return (vdc->vdc_nparity); in vdev_draid_nparity()
2333 vdev_draid_config_t *vdc = vd->vdev_tsd; in vdev_draid_ndisks()
2335 return (vdc->vdc_ndisks); in vdev_draid_ndisks()
2378 vdev_t *vds_draid_vdev; /* top-level parent dRAID vdev */
2379 uint64_t vds_top_guid; /* top-level parent dRAID guid */
2380 uint64_t vds_spare_id; /* spare id (0 - vdc->vdc_nspares-1) */
2390 vdev_draid_spare_t *vds = vd->vdev_tsd; in vdev_draid_spare_get_parent()
2392 ASSERT3P(vd->vdev_ops, ==, &vdev_draid_spare_ops); in vdev_draid_spare_get_parent()
2394 if (vds->vds_draid_vdev != NULL) in vdev_draid_spare_get_parent()
2395 return (vds->vds_draid_vdev); in vdev_draid_spare_get_parent()
2397 return (vdev_lookup_by_guid(vd->vdev_spa->spa_root_vdev, in vdev_draid_spare_get_parent()
2398 vds->vds_top_guid)); in vdev_draid_spare_get_parent()
2408 vdev_t *pvd = vd->vdev_parent; in vdev_draid_spare_is_active()
2410 if (pvd != NULL && (pvd->vdev_ops == &vdev_spare_ops || in vdev_draid_spare_is_active()
2411 pvd->vdev_ops == &vdev_replacing_ops || in vdev_draid_spare_is_active()
2412 pvd->vdev_ops == &vdev_draid_ops)) { in vdev_draid_spare_is_active()
2428 vdev_draid_spare_t *vds = vd->vdev_tsd; in vdev_draid_spare_get_child()
2430 ASSERT3P(vd->vdev_ops, ==, &vdev_draid_spare_ops); in vdev_draid_spare_get_child()
2433 if (vds->vds_draid_vdev == NULL) in vdev_draid_spare_get_child()
2436 vdev_t *tvd = vds->vds_draid_vdev; in vdev_draid_spare_get_child()
2437 vdev_draid_config_t *vdc = tvd->vdev_tsd; in vdev_draid_spare_get_child()
2439 ASSERT3P(tvd->vdev_ops, ==, &vdev_draid_ops); in vdev_draid_spare_get_child()
2440 ASSERT3U(vds->vds_spare_id, <, vdc->vdc_nspares); in vdev_draid_spare_get_child()
2444 uint64_t perm = physical_offset / vdc->vdc_devslicesz; in vdev_draid_spare_get_child()
2449 (tvd->vdev_children - 1) - vds->vds_spare_id); in vdev_draid_spare_get_child()
2450 vdev_t *cvd = tvd->vdev_child[cid]; in vdev_draid_spare_get_child()
2452 if (cvd->vdev_ops == &vdev_draid_spare_ops) in vdev_draid_spare_get_child()
2461 vdev_draid_spare_t *vds = vd->vdev_tsd; in vdev_draid_spare_close()
2462 vds->vds_draid_vdev = NULL; in vdev_draid_spare_close()
2467 * top-level vdev guid from the spare configuration.
2473 vdev_draid_spare_t *vds = vd->vdev_tsd; in vdev_draid_spare_open()
2474 vdev_t *rvd = vd->vdev_spa->spa_root_vdev; in vdev_draid_spare_open()
2477 vdev_t *tvd = vdev_lookup_by_guid(rvd, vds->vds_top_guid); in vdev_draid_spare_open()
2486 if (vd->vdev_parent == NULL) { in vdev_draid_spare_open()
2495 vdev_draid_config_t *vdc = tvd->vdev_tsd; in vdev_draid_spare_open()
2496 if (tvd->vdev_ops != &vdev_draid_ops || vdc == NULL) in vdev_draid_spare_open()
2499 if (vds->vds_spare_id >= vdc->vdc_nspares) in vdev_draid_spare_open()
2503 * Neither tvd->vdev_asize or tvd->vdev_max_asize can be used here in vdev_draid_spare_open()
2514 vds->vds_draid_vdev = tvd; in vdev_draid_spare_open()
2515 vd->vdev_nonrot = tvd->vdev_nonrot; in vdev_draid_spare_open()
2528 zio_t *pio = zio->io_private; in vdev_draid_spare_child_done()
2531 * IOs are issued to non-writable vdevs in order to keep their in vdev_draid_spare_child_done()
2537 if (!vdev_writeable(zio->io_vd)) in vdev_draid_spare_child_done()
2540 if (pio->io_error == 0) in vdev_draid_spare_child_done()
2541 pio->io_error = zio->io_error; in vdev_draid_spare_child_done()
2552 spa_t *spa = vd->vdev_spa; in vdev_draid_read_config_spare()
2553 spa_aux_vdev_t *sav = &spa->spa_spares; in vdev_draid_read_config_spare()
2554 uint64_t guid = vd->vdev_guid; in vdev_draid_read_config_spare()
2557 fnvlist_add_uint64(nv, ZPOOL_CONFIG_IS_SPARE, 1); in vdev_draid_read_config_spare()
2558 fnvlist_add_uint64(nv, ZPOOL_CONFIG_CREATE_TXG, vd->vdev_crtxg); in vdev_draid_read_config_spare()
2562 fnvlist_add_uint64(nv, ZPOOL_CONFIG_POOL_TXG, spa->spa_config_txg); in vdev_draid_read_config_spare()
2563 fnvlist_add_uint64(nv, ZPOOL_CONFIG_TOP_GUID, vd->vdev_top->vdev_guid); in vdev_draid_read_config_spare()
2569 for (int i = 0; i < sav->sav_count; i++) { in vdev_draid_read_config_spare()
2570 if (sav->sav_vdevs[i]->vdev_ops == &vdev_draid_spare_ops && in vdev_draid_read_config_spare()
2571 strcmp(sav->sav_vdevs[i]->vdev_path, vd->vdev_path) == 0) { in vdev_draid_read_config_spare()
2572 guid = sav->sav_vdevs[i]->vdev_guid; in vdev_draid_read_config_spare()
2589 vdev_t *vd = zio->io_vd; in vdev_draid_spare_flush()
2592 for (int c = 0; c < vd->vdev_children; c++) { in vdev_draid_spare_flush()
2594 vd->vdev_child[c], zio->io_offset, zio->io_abd, in vdev_draid_spare_flush()
2595 zio->io_size, zio->io_type, zio->io_priority, 0, in vdev_draid_spare_flush()
2604 * the zio->io_offset and permutation table to calculate which child dRAID vdev
2612 vdev_t *cvd = NULL, *vd = zio->io_vd; in vdev_draid_spare_io_start()
2613 vdev_draid_spare_t *vds = vd->vdev_tsd; in vdev_draid_spare_io_start()
2614 uint64_t offset = zio->io_offset - VDEV_LABEL_START_SIZE; in vdev_draid_spare_io_start()
2621 zio->io_error = ENXIO; in vdev_draid_spare_io_start()
2626 switch (zio->io_type) { in vdev_draid_spare_io_start()
2628 zio->io_error = vdev_draid_spare_flush(zio); in vdev_draid_spare_io_start()
2632 if (VDEV_OFFSET_IS_LABEL(vd, zio->io_offset)) { in vdev_draid_spare_io_start()
2641 if (zio->io_flags & ZIO_FLAG_PROBE || in vdev_draid_spare_io_start()
2642 zio->io_flags & ZIO_FLAG_CONFIG_WRITER) { in vdev_draid_spare_io_start()
2643 zio->io_error = 0; in vdev_draid_spare_io_start()
2645 zio->io_error = SET_ERROR(EIO); in vdev_draid_spare_io_start()
2651 zio->io_error = SET_ERROR(ENXIO); in vdev_draid_spare_io_start()
2654 offset, zio->io_abd, zio->io_size, in vdev_draid_spare_io_start()
2655 zio->io_type, zio->io_priority, 0, in vdev_draid_spare_io_start()
2662 if (VDEV_OFFSET_IS_LABEL(vd, zio->io_offset)) { in vdev_draid_spare_io_start()
2670 if (zio->io_flags & ZIO_FLAG_PROBE) { in vdev_draid_spare_io_start()
2671 zio->io_error = 0; in vdev_draid_spare_io_start()
2673 zio->io_error = SET_ERROR(EIO); in vdev_draid_spare_io_start()
2679 zio->io_error = SET_ERROR(ENXIO); in vdev_draid_spare_io_start()
2682 offset, zio->io_abd, zio->io_size, in vdev_draid_spare_io_start()
2683 zio->io_type, zio->io_priority, 0, in vdev_draid_spare_io_start()
2691 ASSERT0(VDEV_OFFSET_IS_LABEL(vd, zio->io_offset)); in vdev_draid_spare_io_start()
2695 if (cvd == NULL || !cvd->vdev_has_trim) { in vdev_draid_spare_io_start()
2696 zio->io_error = SET_ERROR(ENXIO); in vdev_draid_spare_io_start()
2699 offset, zio->io_abd, zio->io_size, in vdev_draid_spare_io_start()
2700 zio->io_type, zio->io_priority, 0, in vdev_draid_spare_io_start()
2706 zio->io_error = SET_ERROR(ENOTSUP); in vdev_draid_spare_io_start()
2720 * Lookup the full spare config in spa->spa_spares.sav_config and
2731 if ((spa->spa_spares.sav_config == NULL) || in vdev_draid_spare_lookup()
2732 (nvlist_lookup_nvlist_array(spa->spa_spares.sav_config, in vdev_draid_spare_lookup()
2747 /* Skip non-distributed spares */ in vdev_draid_spare_lookup()
2804 vds->vds_draid_vdev = NULL; in vdev_draid_spare_init()
2805 vds->vds_top_guid = top_guid; in vdev_draid_spare_init()
2806 vds->vds_spare_id = spare_id; in vdev_draid_spare_init()
2816 kmem_free(vd->vdev_tsd, sizeof (vdev_draid_spare_t)); in vdev_draid_spare_fini()
2822 vdev_draid_spare_t *vds = vd->vdev_tsd; in vdev_draid_spare_config_generate()
2824 ASSERT3P(vd->vdev_ops, ==, &vdev_draid_spare_ops); in vdev_draid_spare_config_generate()
2826 fnvlist_add_uint64(nv, ZPOOL_CONFIG_TOP_GUID, vds->vds_top_guid); in vdev_draid_spare_config_generate()
2827 fnvlist_add_uint64(nv, ZPOOL_CONFIG_SPARE_ID, vds->vds_spare_id); in vdev_draid_spare_config_generate()