Lines Matching +full:0 +full:x27c
169 #define DTSEC_IMASK_BREN 0x80000000
170 #define DTSEC_IMASK_RXCEN 0x40000000
171 #define DTSEC_IMASK_MSROEN 0x04000000
172 #define DTSEC_IMASK_GTSCEN 0x02000000
173 #define DTSEC_IMASK_BTEN 0x01000000
174 #define DTSEC_IMASK_TXCEN 0x00800000
175 #define DTSEC_IMASK_TXEEN 0x00400000
176 #define DTSEC_IMASK_LCEN 0x00040000
177 #define DTSEC_IMASK_CRLEN 0x00020000
178 #define DTSEC_IMASK_XFUNEN 0x00010000
179 #define DTSEC_IMASK_ABRTEN 0x00008000
180 #define DTSEC_IMASK_IFERREN 0x00004000
181 #define DTSEC_IMASK_MAGEN 0x00000800
182 #define DTSEC_IMASK_MMRDEN 0x00000400
183 #define DTSEC_IMASK_MMWREN 0x00000200
184 #define DTSEC_IMASK_GRSCEN 0x00000100
185 #define DTSEC_IMASK_TDPEEN 0x00000002
186 #define DTSEC_IMASK_RDPEEN 0x00000001
204 #define TMR_PEMASK_TSREEN 0x00010000
205 #define TMR_PEVENT_TSRE 0x00010000
208 #define MAC_GROUP_ADDRESS 0x0000010000000000ULL
213 #define DEFAULT_HALFDUP_RETRANSMIT 0xf
214 #define DEFAULT_HALFDUP_COLL_WINDOW 0x37
218 #define DEFAULT_HALFDUP_ALT_BACKOFF_VAL 0x0A
226 #define DEFAULT_TX_PAUSE_TIME 0xf000
228 #define DEFAULT_RX_PREPEND 0
240 #define DEFAULT_TX_PAUSE_TIME_EXTD 0
242 #define DEFAULT_NON_BACK_TO_BACK_IPG1 0x40
243 #define DEFAULT_NON_BACK_TO_BACK_IPG2 0x60
244 #define DEFAULT_MIN_IFG_ENFORCEMENT 0x50
245 #define DEFAULT_BACK_TO_BACK_IPG 0x60
246 #define DEFAULT_MAXIMUM_FRAME 0x600
251 #define DTSEC_ID1_ID 0xffff0000
252 #define DTSEC_ID1_REV_MJ 0x0000FF00
253 #define DTSEC_ID1_REV_MN 0x000000ff
255 #define DTSEC_ID2_INT_REDUCED_OFF 0x00010000
256 #define DTSEC_ID2_INT_NORMAL_OFF 0x00020000
258 #define DTSEC_ECNTRL_CLRCNT 0x00004000
259 #define DTSEC_ECNTRL_AUTOZ 0x00002000
260 #define DTSEC_ECNTRL_STEN 0x00001000
261 #define DTSEC_ECNTRL_CFG_RO 0x80000000
262 #define DTSEC_ECNTRL_GMIIM 0x00000040
263 #define DTSEC_ECNTRL_TBIM 0x00000020
264 #define DTSEC_ECNTRL_SGMIIM 0x00000002
265 #define DTSEC_ECNTRL_RPM 0x00000010
266 #define DTSEC_ECNTRL_R100M 0x00000008
267 #define DTSEC_ECNTRL_RMM 0x00000004
268 #define DTSEC_ECNTRL_QSGMIIM 0x00000001
270 #define DTSEC_TCTRL_THDF 0x00000800
271 #define DTSEC_TCTRL_TTSE 0x00000040
272 #define DTSEC_TCTRL_GTS 0x00000020
273 #define DTSEC_TCTRL_TFC_PAUSE 0x00000010
278 #define RCTRL_CFA 0x00008000
279 #define RCTRL_GHTX 0x00000400
280 #define RCTRL_RTSE 0x00000040
281 #define RCTRL_GRS 0x00000020
282 #define RCTRL_BC_REJ 0x00000010
283 #define RCTRL_MPROM 0x00000008
284 #define RCTRL_RSF 0x00000004
285 #define RCTRL_UPROM 0x00000001
288 #define TMR_CTL_ESFDP 0x00000800
289 #define TMR_CTL_ESFDE 0x00000400
291 #define MACCFG1_SOFT_RESET 0x80000000
292 #define MACCFG1_LOOPBACK 0x00000100
293 #define MACCFG1_RX_FLOW 0x00000020
294 #define MACCFG1_TX_FLOW 0x00000010
295 #define MACCFG1_TX_EN 0x00000001
296 #define MACCFG1_RX_EN 0x00000004
297 #define MACCFG1_RESET_RxMC 0x00080000
298 #define MACCFG1_RESET_TxMC 0x00040000
299 #define MACCFG1_RESET_RxFUN 0x00020000
300 #define MACCFG1_RESET_TxFUN 0x00010000
302 #define MACCFG2_NIBBLE_MODE 0x00000100
303 #define MACCFG2_BYTE_MODE 0x00000200
304 #define MACCFG2_PRE_AM_Rx_EN 0x00000080
305 #define MACCFG2_PRE_AM_Tx_EN 0x00000040
306 #define MACCFG2_LENGTH_CHECK 0x00000010
307 #define MACCFG2_MAGIC_PACKET_EN 0x00000008
308 #define MACCFG2_PAD_CRC_EN 0x00000004
309 #define MACCFG2_CRC_EN 0x00000002
310 #define MACCFG2_FULL_DUPLEX 0x00000001
318 #define IPGIFG_NON_BACK_TO_BACK_IPG_1 0x7F000000
319 #define IPGIFG_NON_BACK_TO_BACK_IPG_2 0x007F0000
320 #define IPGIFG_MIN_IFG_ENFORCEMENT 0x0000FF00
321 #define IPGIFG_BACK_TO_BACK_IPG 0x0000007F
323 #define HAFDUP_ALT_BEB 0x00080000
324 #define HAFDUP_BP_NO_BACKOFF 0x00040000
325 #define HAFDUP_NO_BACKOFF 0x00020000
326 #define HAFDUP_EXCESS_DEFER 0x00010000
327 #define HAFDUP_COLLISION_WINDOW 0x000003ff
331 #define HAFDUP_RETRANSMISSION_MAX 0x0000f000
336 #define DTSEC_CAR1_TR64 0x80000000
337 #define DTSEC_CAR1_TR127 0x40000000
338 #define DTSEC_CAR1_TR255 0x20000000
339 #define DTSEC_CAR1_TR511 0x10000000
340 #define DTSEC_CAR1_TRK1 0x08000000
341 #define DTSEC_CAR1_TRMAX 0x04000000
342 #define DTSEC_CAR1_TRMGV 0x02000000
344 #define DTSEC_CAR1_RBYT 0x00010000
345 #define DTSEC_CAR1_RPKT 0x00008000
346 #define DTSEC_CAR1_RFCS 0x00004000
347 #define DTSEC_CAR1_RMCA 0x00002000
348 #define DTSEC_CAR1_RBCA 0x00001000
349 #define DTSEC_CAR1_RXCF 0x00000800
350 #define DTSEC_CAR1_RXPF 0x00000400
351 #define DTSEC_CAR1_RXUO 0x00000200
352 #define DTSEC_CAR1_RALN 0x00000100
353 #define DTSEC_CAR1_RFLR 0x00000080
354 #define DTSEC_CAR1_RCDE 0x00000040
355 #define DTSEC_CAR1_RCSE 0x00000020
356 #define DTSEC_CAR1_RUND 0x00000010
357 #define DTSEC_CAR1_ROVR 0x00000008
358 #define DTSEC_CAR1_RFRG 0x00000004
359 #define DTSEC_CAR1_RJBR 0x00000002
360 #define DTSEC_CAR1_RDRP 0x00000001
362 #define DTSEC_CAR2_TJBR 0x00080000
363 #define DTSEC_CAR2_TFCS 0x00040000
364 #define DTSEC_CAR2_TXCF 0x00020000
365 #define DTSEC_CAR2_TOVR 0x00010000
366 #define DTSEC_CAR2_TUND 0x00008000
367 #define DTSEC_CAR2_TFRG 0x00004000
368 #define DTSEC_CAR2_TBYT 0x00002000
369 #define DTSEC_CAR2_TPKT 0x00001000
370 #define DTSEC_CAR2_TMCA 0x00000800
371 #define DTSEC_CAR2_TBCA 0x00000400
372 #define DTSEC_CAR2_TXPF 0x00000200
373 #define DTSEC_CAR2_TDFR 0x00000100
374 #define DTSEC_CAR2_TEDF 0x00000080
375 #define DTSEC_CAR2_TSCL 0x00000040
376 #define DTSEC_CAR2_TMCL 0x00000020
377 #define DTSEC_CAR2_TLCL 0x00000010
378 #define DTSEC_CAR2_TXCL 0x00000008
379 #define DTSEC_CAR2_TNCL 0x00000004
380 #define DTSEC_CAR2_TDRP 0x00000001
407 uint32_t tsec_id; /* 0x000 ETSEC_ID register */
408 uint32_t tsec_id2; /* 0x004 ETSEC_ID2 register */
409 uint32_t ievent; /* 0x008 Interrupt event register */
410 uint32_t imask; /* 0x00C Interrupt mask register */
412 uint32_t ecntrl; /* 0x014 E control register */
413 uint32_t ptv; /* 0x018 Pause time value register */
414 uint32_t tbipa; /* 0x01C TBI PHY address register */
415 uint32_t tmr_ctrl; /* 0x020 Time-stamp Control register */
416 uint32_t tmr_pevent; /* 0x024 Time-stamp event register */
417 uint32_t tmr_pemask; /* 0x028 Timer event mask register */
419 uint32_t tctrl; /* 0x040 Transmit control register */
421 uint32_t rctrl; /* 0x050 Receive control register */
423 uint32_t igaddr[8]; /* 0x080-0x09C Individual/group address */
424 uint32_t gaddr[8]; /* 0x0A0-0x0BC Group address registers 0-7 */
426 uint32_t maccfg1; /* 0x100 MAC configuration #1 */
427 uint32_t maccfg2; /* 0x104 MAC configuration #2 */
428 uint32_t ipgifg; /* 0x108 IPG/IFG */
429 uint32_t hafdup; /* 0x10C Half-duplex */
430 uint32_t maxfrm; /* 0x110 Maximum frame */
432 uint32_t ifstat; /* 0x13C Interface status */
433 uint32_t macstnaddr1; /* 0x140 Station Address,part 1 */
434 uint32_t macstnaddr2; /* 0x144 Station Address,part 2 */
438 } macaddr[15]; /* 0x148-0x1BC mac exact match addresses 1-15 */
440 uint32_t tr64; /* 0x200 transmit and receive 64 byte frame counter */
441 uint32_t tr127; /* 0x204 transmit and receive 65 to 127 byte frame
443 uint32_t tr255; /* 0x208 transmit and receive 128 to 255 byte frame
445 uint32_t tr511; /* 0x20C transmit and receive 256 to 511 byte frame
447 uint32_t tr1k; /* 0x210 transmit and receive 512 to 1023 byte frame
449 uint32_t trmax; /* 0x214 transmit and receive 1024 to 1518 byte frame
451 uint32_t trmgv; /* 0x218 transmit and receive 1519 to 1522 byte good
453 uint32_t rbyt; /* 0x21C receive byte counter */
454 uint32_t rpkt; /* 0x220 receive packet counter */
455 uint32_t rfcs; /* 0x224 receive FCS error counter */
456 uint32_t rmca; /* 0x228 RMCA receive multicast packet counter */
457 uint32_t rbca; /* 0x22C receive broadcast packet counter */
458 uint32_t rxcf; /* 0x230 receive control frame packet counter */
459 uint32_t rxpf; /* 0x234 receive pause frame packet counter */
460 uint32_t rxuo; /* 0x238 receive unknown OP code counter */
461 uint32_t raln; /* 0x23C receive alignment error counter */
462 uint32_t rflr; /* 0x240 receive frame length error counter */
463 uint32_t rcde; /* 0x244 receive code error counter */
464 uint32_t rcse; /* 0x248 receive carrier sense error counter */
465 uint32_t rund; /* 0x24C receive undersize packet counter */
466 uint32_t rovr; /* 0x250 receive oversize packet counter */
467 uint32_t rfrg; /* 0x254 receive fragments counter */
468 uint32_t rjbr; /* 0x258 receive jabber counter */
469 uint32_t rdrp; /* 0x25C receive drop */
470 uint32_t tbyt; /* 0x260 transmit byte counter */
471 uint32_t tpkt; /* 0x264 transmit packet counter */
472 uint32_t tmca; /* 0x268 transmit multicast packet counter */
473 uint32_t tbca; /* 0x26C transmit broadcast packet counter */
474 uint32_t txpf; /* 0x270 transmit pause control frame counter */
475 uint32_t tdfr; /* 0x274 transmit deferral packet counter */
476 uint32_t tedf; /* 0x278 transmit excessive deferral packet counter */
477 uint32_t tscl; /* 0x27C transmit single collision packet counter */
478 uint32_t tmcl; /* 0x280 transmit multiple collision packet counter */
479 uint32_t tlcl; /* 0x284 transmit late collision packet counter */
480 uint32_t txcl; /* 0x288 transmit excessive collision packet counter */
481 uint32_t tncl; /* 0x28C transmit total collision counter */
483 uint32_t tdrp; /* 0x294 transmit drop frame counter */
484 uint32_t tjbr; /* 0x298 transmit jabber frame counter */
485 uint32_t tfcs; /* 0x29C transmit FCS error counter */
486 uint32_t txcf; /* 0x2A0 transmit control frame counter */
487 uint32_t tovr; /* 0x2A4 transmit oversize frame counter */
488 uint32_t tund; /* 0x2A8 transmit undersize frame counter */
489 uint32_t tfrg; /* 0x2AC transmit fragments frame counter */
490 uint32_t car1; /* 0x2B0 carry register one register* */
491 uint32_t car2; /* 0x2B4 carry register two register* */
492 uint32_t cam1; /* 0x2B8 carry register one mask register */
493 uint32_t cam2; /* 0x2BC carry register two mask register */
620 E_MAC_STAT_NONE = 0,
665 * that have an ethertype of 0x8808 are treated as normal
672 * frame is initiated. If set to 0 this disables
684 * value of 0x7 should be used in order to guarantee
766 * Returns: 0 if successful, an error code otherwise.
857 * Returns: 0 if successful, an error code otherwise.
866 * @address: Valid PHY address in the range of 1 to 31. 0 is reserved.
871 * Returns: 0 if successful, an error code otherwise.
913 * If time is 0, transmission of pause frames is disabled