Lines Matching +full:auto +full:- +full:retry
2 * Copyright 2008-2012 Freescale Semiconductor Inc.
37 @Description Ethernet MAC-PHY Interface
72 @Description Enum for inter-module interrupts registration
152 /**< dTSEC Collision retry limit */
168 /**< dTSEC Time-Stamp Receive Error */
172 /**< mEMAC Time-stamp FIFO ECC error interrupt;
177 /**< SGMII/QSGII interface with 1000BaseX auto-negotiation between MAC
179 Note: 1000BaseX auto-negotiation relates only to interface between MAC
180 and phy/backplane, SGMII phy can still synchronize with far-end phy at
211 /**< 10 Mbps SGMII with auto-negotiation between MAC and
214 /**< 100 Mbps SGMII with auto-negotiation between MAC and
217 /**< 1000 Mbps SGMII with auto-negotiation between MAC and
221 /**< 10 Mbps SGMII with 1000BaseX auto-negotiation between
225 /**< 100 Mbps SGMII with 1000BaseX auto-negotiation between
229 /**< 1000 Mbps SGMII with 1000BaseX auto-negotiation between
232 /**< 1000 Mbps QSGMII with auto-negotiation between MAC and
236 /**< 1000 Mbps QSGMII with 1000BaseX auto-negotiation between
270 (_enet_addr)[i] = (uint8_t)((_addr64) >> ((5-i)*8));\