Lines Matching full:volatile
177 volatile uint32_t lio_cfg; /**< QMan Software Portal LIO Configuration */
178 volatile uint32_t io_cfg; /**< QMan Software Portal 0 IO Configuration */
179 volatile uint8_t res1[4]; /**< reserved */
180 … volatile uint32_t dd_cfg; /**< Software Portal Dynamic Debug Configuration */
182 volatile uint8_t res1[352]; /**< reserved */
185 volatile uint32_t qman_dd_cfg; /**< QMan Dynamic Debug (DD) Configuration */
186 volatile uint8_t res2[12]; /**< reserved */
187 …volatile uint32_t qcsp_dd_ihrsr; /**< Software Portal DD Internal Halt Request Stat…
188 …volatile uint32_t qcsp_dd_ihrfr; /**< Software Portal DD Internal Halt Request Forc…
189 … volatile uint32_t qcsp_dd_hasr; /**< Software Portal DD Halt Acknowledge Status */
190 volatile uint8_t res3[4]; /**< reserved */
191 volatile uint32_t dcp_dd_ihrsr; /**< DCP DD Internal Halt Request Status */
192 volatile uint32_t dcp_dd_ihrfr; /**< DCP DD Internal Halt Request Force */
193 volatile uint32_t dcp_dd_hasr; /**< DCP DD Halt Acknowledge Status */
194 volatile uint8_t res4[212]; /**< reserved */
198 volatile uint32_t cfg; /**< DCP Configuration */
199 volatile uint32_t dd_cfg; /**< DCP Dynamic Debug Configuration */
200 … volatile uint32_t dlm_cfg; /**< DCP Dequeue Latency Monitor Configuration */
201 volatile uint32_t dlm_avg; /**< DCP Dequeue Latency Monitor Average */
203 volatile uint8_t res5[176]; /**< reserved */
206 volatile uint32_t pfdr_fpc; /**< PFDR Free Pool Count */
207 volatile uint32_t pfdr_fp_head; /**< PFDR Free Pool Head Pointer */
208 volatile uint32_t pfdr_fp_tail; /**< PFDR Free Pool Tail Pointer */
209 volatile uint8_t res6[4]; /**< reserved */
210 …volatile uint32_t pfdr_fp_lwit; /**< PFDR Free Pool Low Watermark Interrupt Thresh…
211 volatile uint32_t pfdr_cfg; /**< PFDR Configuration */
212 volatile uint8_t res7[232]; /**< reserved */
215 volatile uint32_t sfdr_cfg; /**< SFDR Configuration */
216 volatile uint32_t sfdr_in_use; /**< SFDR In Use Register */
217 volatile uint8_t res8[248]; /**< reserved */
220 volatile uint32_t wq_cs_cfg[6]; /**< Work Queue Class Scheduler Configuration */
221 volatile uint8_t res9[24]; /**< reserved */
222 volatile uint32_t wq_def_enq_wqid; /**< Work Queue Default Enqueue WQID */
223 volatile uint8_t res10[12]; /**< reserved */
224 volatile uint32_t wq_sc_dd_cfg[5]; /**< WQ S/W Channel Dynamic Debug Config */
225 volatile uint8_t res11[44]; /**< reserved */
226 volatile uint32_t wq_pc_dd_cs_cfg[8]; /**< WQ Pool Channel Dynamic Debug Config */
227 volatile uint8_t res12[32]; /**< reserved */
228 volatile uint32_t wq_dc0_dd_cs_cfg[6]; /**< WQ DCP0 Chan. Dynamic Debug Config */
229 volatile uint8_t res13[40]; /**< reserved */
230 volatile uint32_t wq_dc1_dd_cs_cfg[6]; /**< WQ DCP1 Chan. Dynamic Debug Config */
231 volatile uint8_t res14[40]; /**< reserved */
232 volatile uint32_t wq_dc2_dd_cs_cfg; /**< WQ DCP2 Chan. Dynamic Debug Config */
233 volatile uint8_t res15[60]; /**< reserved */
234 volatile uint32_t wq_dc3_dd_cs_cfg; /**< WQ DCP3 Chan. Dynamic Debug Config */
235 volatile uint8_t res16[124]; /**< reserved */
238 volatile uint32_t cm_cfg; /**< CM Configuration Register */
239 volatile uint8_t res17[508]; /**< reserved */
242 volatile uint32_t ecsr; /**< QMan Error Capture Status Register */
243 volatile uint32_t ecir; /**< QMan Error Capture Information Register */
244 volatile uint32_t eadr; /**< QMan Error Capture Address Register */
245 volatile uint8_t res18[4]; /**< reserved */
246 volatile uint32_t edata[16]; /**< QMan ECC Error Data Register */
247 volatile uint8_t res19[32]; /**< reserved */
248 …volatile uint32_t sbet; /**< QMan Single Bit ECC Error Threshold Register …
249 volatile uint8_t res20[12]; /**< reserved */
250 volatile uint32_t sbec[7]; /**< QMan Single Bit ECC Error Count Register */
251 volatile uint8_t res21[100]; /**< reserved */
254 volatile uint32_t mcr; /**< QMan Management Command/Result Register */
255 …volatile uint32_t mcp0; /**< QMan Management Command Parameter 0 Register …
256 …volatile uint32_t mcp1; /**< QMan Management Command Parameter 1 Register …
257 volatile uint8_t res22[20]; /**< reserved */
258 volatile uint32_t mr[16]; /**< QMan Management Return Register */
259 volatile uint8_t res23[148]; /**< reserved */
260 volatile uint32_t idle_stat; /**< QMan Idle Status Register */
263 volatile uint32_t ip_rev_1; /**< QMan IP Block Revision 1 register */
264 volatile uint32_t ip_rev_2; /**< QMan IP Block Revision 2 register */
267 volatile uint32_t fqd_bare; /**< FQD Extended Base Address Register */
268 …volatile uint32_t fqd_bar; /**< Frame Queue Descriptor (FQD) Base Address Reg…
269 volatile uint8_t res24[8]; /**< reserved */
270 volatile uint32_t fqd_ar; /**< FQD Attributes Register */
271 volatile uint8_t res25[12]; /**< reserved */
272 volatile uint32_t pfdr_bare; /**< PFDR Extended Base Address Register */
273 …volatile uint32_t pfdr_bar; /**< Packed Frame Descriptor Record (PFDR) Base Ad…
274 volatile uint8_t res26[8]; /**< reserved */
275 volatile uint32_t pfdr_ar; /**< PFDR Attributes Register */
276 volatile uint8_t res27[76]; /**< reserved */
277 volatile uint32_t qcsp_bare; /**< QCSP Extended Base Address */
278 volatile uint32_t qcsp_bar; /**< QMan Software Portal Base Address */
279 volatile uint8_t res28[120]; /**< reserved */
280 volatile uint32_t ci_sched_cfg; /**< Initiator Scheduling Configuration */
281 volatile uint32_t srcidr; /**< QMan Source ID Register */
282 volatile uint32_t liodnr; /**< QMan Logical I/O Device Number Register */
283 volatile uint8_t res29[4]; /**< reserved */
284 …volatile uint32_t ci_rlm_cfg; /**< Initiator Read Latency Monitor Configuration …
285 volatile uint32_t ci_rlm_avg; /**< Initiator Read Latency Monitor Average */
286 volatile uint8_t res30[232]; /**< reserved */
289 volatile uint32_t err_isr; /**< QMan Error Interrupt Status Register */
290 volatile uint32_t err_ier; /**< QMan Error Interrupt Enable Register */
291 …volatile uint32_t err_isdr; /**< QMan Error Interrupt Status Disable Register …
292 volatile uint32_t err_iir; /**< QMan Error Interrupt Inhibit Register */
293 volatile uint8_t res31[4]; /**< reserved */
294 volatile uint32_t err_her; /**< QMan Error Halt Enable Register */
538 volatile int disable_count;