Lines Matching +full:non +full:- +full:volatile
3 � 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
50 /* QMan s/w corenet portal, low-level i/face */
53 e_QmPortalPCI = 0, /* PI index, cache-inhibited */
54 e_QmPortalPCE, /* PI index, cache-enabled */
55 e_QmPortalPVB /* valid-bit */
59 e_QmPortalEqcrCCI = 0, /* CI index, cache-inhibited */
60 e_QmPortalEqcrCCE /* CI index, cache-enabled */
64 e_QmPortalDqrrCCI = 0, /* CI index, cache-inhibited */
65 e_QmPortalDqrrCCE, /* CI index, cache-enabled */
70 e_QmPortalMrCCI = 0, /* CI index, cache-inhibited */
71 e_QmPortalMrCCE /* CI index, cache-enabled */
115 * also used for any "core-affine" portals, ie. default portals
116 * associated to the corresponding cpu. -1 implies that there is no core
127 /* which portal sub-interfaces are already bound (ie. "in use") */
144 /* Bitmask of portal (logical-, not cell-)indices that have dequeue
146 * 0x001 -> qm_portal_get(0)
147 * 0x002 -> qm_portal_get(1)
148 * 0x004 -> qm_portal_get(2)
150 * 0x200 -> qm_portal_get(9)
155 /* ------------------------------ */
156 /* --- Portal enumeration API --- */
165 /* ------------------------------------ */
166 /* --- Pool channel enumeration API --- */
173 * bit-mask (the least significant bit of 'mask' is used if more than one bit is
193 #define QM_SDQCR_TYPE_SET(v) (((v) & 0x03) << (31-7))
206 * NUMFRAMES(n) (6-bit) or NUMFRAMES_TILLEMPTY to fill in the frame-count. Use
226 * Either select the work-queue ID with SPECIFICWQ_WQ(), or select the
228 * work-queue priority (0-7) with SPECIFICWQ_WQ() - either way, you get the
253 /* ------------------------------------- */
254 /* --- Portal interrupt register API --- */
260 * and while there are truly-scheduled FQs available, it is deasserted as/when
261 * there are no longer any truly-scheduled FQs available. The same is true for
267 * asserted in the status register, it must be write-1-to-clear'd - the
273 * status register can still reveal un-enabled bits - this is why the
275 * "Un-enabled" means it won't, on its own, trigger an interrupt.
279 * zero. The inhibit register is the only interrupt-related register that
280 * does not share the bit definitions - it is a boolean on/off register.
289 #define QM_PIRQ_DQRI 0x00020000 /* DQRR Ring (non-empty) */
290 #define QM_PIRQ_MRI 0x00010000 /* MR Ring (non-empty) */
307 /* ------------------------------------------------------- */
308 /* --- Qman data structures (and associated constants) --- */
316 * scatter-gather table. 'big' implies a 29-bit length with no offset
317 * field, otherwise length is 20-bit and offset is 9-bit. 'compound'
318 * implies a s/g-like table, where each entry itself represents a frame
319 * (contiguous or scatter-gather) and the 29-bit "length" is
336 volatile uint8_t exclusive;
337 volatile uint8_t reserved1:2;
339 volatile uint8_t annotation_cl:2;
340 volatile uint8_t data_cl:2;
341 volatile uint8_t context_cl:2;
345 /* Treat it as 64-bit opaque */
347 volatile uint32_t hi;
348 volatile uint32_t lo;
354 volatile uint8_t reserved1;
355 /* 40-bit address of FQ context to
356 * stash, must be cacheline-aligned */
357 volatile uint8_t context_hi;
358 volatile uint32_t context_lo;
364 volatile uint8_t dd:2; /* dynamic debug */
365 volatile uint8_t liodn_offset:6; /* aka. "Partition ID" in rev1.0 */
366 volatile uint8_t bpid; /* Buffer Pool ID */
367 volatile uint8_t eliodn_offset:4;
368 volatile uint8_t reserved:4;
369 volatile uint8_t addr_hi; /* high 8-bits of 40-bit address */
370 volatile uint32_t addr_lo; /* low 32-bits of 40-bit address */
372 * bits of the 32-bit word. For packing reasons, it is duplicated in the
377 volatile enum qm_fd_format format:3;
378 volatile uint16_t offset:9;
379 volatile uint32_t length20:20;
383 volatile enum qm_fd_format _format1:3;
384 volatile uint32_t length29:29;
388 volatile enum qm_fd_format _format2:3;
389 volatile uint32_t cong_weight:29;
393 volatile uint32_t opaque;
396 volatile uint32_t cmd;
397 volatile uint32_t status;
406 volatile uint8_t __dont_write_directly__verb;
407 volatile uint8_t dca;
408 volatile uint16_t seqnum;
409 volatile uint32_t orp; /* 24-bit */
410 volatile uint32_t fqid; /* 24-bit */
411 volatile uint32_t tag;
412 volatile struct qm_fd fd;
413 volatile uint8_t reserved3[32];
436 volatile uint8_t verb;
437 volatile uint8_t stat;
438 volatile uint16_t seqnum; /* 15-bit */
439 volatile uint8_t tok;
440 volatile uint8_t reserved2[3];
441 volatile uint32_t fqid; /* 24-bit */
442 volatile uint32_t contextB;
443 volatile struct qm_fd fd;
444 volatile uint8_t reserved4[32];
452 #define QM_DQRR_STAT_FQ_FORCEELIGIBLE 0x20 /* FQ was force-eligible'd */
453 #define QM_DQRR_STAT_FD_VALID 0x10 /* has a non-NULL FD */
463 volatile uint8_t verb;
466 volatile uint8_t dca;
467 volatile uint16_t seqnum;
468 volatile uint8_t rc; /* Rejection Code */
469 volatile uint32_t orp:24;
470 volatile uint32_t fqid; /* 24-bit */
471 volatile uint32_t tag;
472 volatile struct qm_fd fd;
475 volatile uint8_t colour:2; /* See QM_MR_DCERN_COLOUR_* */
476 volatile uint8_t reserved1:3;
477 volatile enum qm_dc_portal portal:3;
478 volatile uint16_t reserved2;
479 volatile uint8_t rc; /* Rejection Code */
480 volatile uint32_t reserved3:24;
481 volatile uint32_t fqid; /* 24-bit */
482 volatile uint32_t tag;
483 volatile struct qm_fd fd;
486 volatile uint8_t fqs; /* Frame Queue Status */
487 volatile uint8_t reserved1[6];
488 volatile uint32_t fqid; /* 24-bit */
489 volatile uint32_t contextB;
490 volatile uint8_t reserved2[16];
493 volatile uint8_t reserved2[32];
498 * originating from direct-connect portals ("dcern") use 0x20 as a verb which
525 * also used as the qman_query_fq() result structure in the high-level API. */
527 /* TODO What about OAC for intra-class? */
532 volatile uint8_t orpc;
534 volatile uint8_t reserved1:2;
535 volatile uint8_t orprws:3;
536 volatile uint8_t oa:1;
537 volatile uint8_t olws:2;
540 volatile uint8_t cgid;
541 volatile uint16_t fq_ctrl; /* See QM_FQCTRL_<...> */
543 volatile uint16_t dest_wq;
545 volatile uint16_t channel:13; /* enum qm_channel */
546 volatile uint16_t wq:3;
549 volatile uint16_t reserved2:1;
550 volatile uint16_t ics_cred:15;
552 volatile uint16_t td_thresh;
554 volatile uint16_t reserved1:3;
555 volatile uint16_t mant:8;
556 volatile uint16_t exp:5;
559 volatile uint32_t context_b;
560 volatile u_QmFqdContextA context_a;
567 #define QM_FQCTRL_TDE 0x0200 /* Tail-Drop Enable */
569 #define QM_FQCTRL_CTXASTASHING 0x0080 /* Context-A stashing */
571 #define QM_FQCTRL_FORCESFDR 0x0008 /* High-priority SFDRs */
583 /* This struct represents the 32-bit "WR_PARM_[GYR]" parameters in CGR fields
592 volatile uint32_t word;
594 volatile uint32_t MA:8;
595 volatile uint32_t Mn:5;
596 volatile uint32_t SA:7; /* must be between 64-127 */
597 volatile uint32_t Sn:6;
598 volatile uint32_t Pn:6;
603 /* This struct represents the 13-bit "CS_THRES" CGR field. In the corresponding
604 * management commands, this is padded to a 16-bit structure field, so that's
610 volatile uint16_t reserved:3;
611 volatile uint16_t TA:8;
612 volatile uint16_t Tn:5;
619 volatile struct qm_cgr_wr_parm wr_parm_g;
620 volatile struct qm_cgr_wr_parm wr_parm_y;
621 volatile struct qm_cgr_wr_parm wr_parm_r;
622 volatile uint8_t wr_en_g; /* boolean, use QM_CGR_EN */
623 volatile uint8_t wr_en_y; /* boolean, use QM_CGR_EN */
624 volatile uint8_t wr_en_r; /* boolean, use QM_CGR_EN */
625 volatile uint8_t cscn_en; /* boolean, use QM_CGR_EN */
626 volatile uint32_t cscn_targ; /* use QM_CGR_TARG_* */
627 volatile uint8_t cstd_en; /* boolean, use QM_CGR_EN */
628 volatile uint8_t cs; /* boolean, only used in query response */
629 volatile struct qm_cgr_cs_thres cs_thres;
630 volatile uint8_t frame_mode; /* boolean, use QM_CGR_EN */
637 /* See 1.5.8.5.3: "Query FQ Non-Programmable Fields" */
643 volatile uint8_t __dont_write_directly__verb;
646 volatile uint8_t reserved1;
647 volatile uint16_t we_mask; /* Write Enable Mask */
648 volatile uint32_t fqid; /* 24-bit */
649 volatile uint16_t count; /* Initialises 'count+1' FQDs */
650 volatile struct qm_fqd fqd; /* the FQD fields go here */
651 volatile uint8_t reserved3[32];
654 volatile uint8_t reserved1[3];
655 volatile uint32_t fqid; /* 24-bit */
656 volatile uint8_t reserved2[56];
659 volatile uint8_t reserved1[3];
660 volatile uint32_t fqid; /* 24-bit */
661 volatile uint8_t reserved2[56];
664 volatile uint8_t reserved1[3];
665 volatile uint32_t fqid; /* 24-bit */
666 volatile uint8_t reserved2[12];
667 volatile uint32_t context_b;
668 volatile uint8_t reserved3[40];
671 volatile uint8_t reserved1;
672 volatile uint16_t we_mask; /* Write Enable Mask */
673 volatile struct __qm_mc_cgr cgr; /* CGR fields */
674 volatile uint8_t reserved2[2];
675 volatile uint8_t cgid;
676 volatile uint8_t reserved4[32];
679 volatile uint8_t reserved1[30];
680 volatile uint8_t cgid;
681 volatile uint8_t reserved2[32];
684 volatile uint8_t reserved[63];
687 volatile uint8_t reserved;
690 volatile uint16_t channel_wq; /* ignores wq (3 lsbits) */
692 volatile uint16_t id:13; /* enum qm_channel */
693 volatile uint16_t reserved1:3;
696 volatile uint8_t reserved2[60];
706 #define QM_MCC_VERB_QUERYFQ_NP 0x45 /* "non-programmable" fields */
718 /* INITFQ-specific flags */
729 /* INITCGR/MODIFYCGR-specific flags */
745 /* See 1.5.8.5.3: "Query FQ Non-Programmable Fields" */
751 volatile uint8_t verb;
752 volatile uint8_t result;
755 volatile uint8_t reserved1[62];
758 volatile uint8_t reserved1[8];
759 volatile struct qm_fqd fqd; /* the FQD fields are here */
760 volatile uint16_t oac;
761 volatile uint8_t reserved2[30];
764 volatile uint8_t reserved1;
765 volatile uint8_t state; /* QM_MCR_NP_STATE_*** */
766 volatile uint8_t reserved2;
767 volatile uint32_t fqd_link:24;
768 volatile uint16_t odp_seq;
769 volatile uint16_t orp_nesn;
770 volatile uint16_t orp_ea_hseq;
771 volatile uint16_t orp_ea_tseq;
772 volatile uint8_t reserved3;
773 volatile uint32_t orp_ea_hptr:24;
774 volatile uint8_t reserved4;
775 volatile uint32_t orp_ea_tptr:24;
776 volatile uint8_t reserved5;
777 volatile uint32_t pfdr_hptr:24;
778 volatile uint8_t reserved6;
779 volatile uint32_t pfdr_tptr:24;
780 volatile uint8_t reserved7[5];
781 volatile uint8_t reserved8:7;
782 volatile uint8_t is:1;
783 volatile uint16_t ics_surp;
784 volatile uint32_t byte_cnt;
785 volatile uint8_t reserved9;
786 volatile uint32_t frm_cnt:24;
787 volatile uint32_t reserved10;
788 volatile uint16_t ra1_sfdr; /* QM_MCR_NP_RA1_*** */
789 volatile uint16_t ra2_sfdr; /* QM_MCR_NP_RA2_*** */
790 volatile uint16_t reserved11;
791 volatile uint16_t od1_sfdr; /* QM_MCR_NP_OD1_*** */
792 volatile uint16_t od2_sfdr; /* QM_MCR_NP_OD2_*** */
793 volatile uint16_t od3_sfdr; /* QM_MCR_NP_OD3_*** */
796 volatile uint8_t fqs; /* Frame Queue Status */
797 volatile uint8_t reserved1[61];
800 volatile uint8_t reserved1[62];
803 volatile uint16_t reserved1;
804 volatile struct __qm_mc_cgr cgr; /* CGR fields */
805 volatile uint8_t reserved2[3];
806 volatile uint32_t reserved3:24;
807 volatile uint32_t i_bcnt_hi:8;/* high 8-bits of 40-bit "Instant" */
808 volatile uint32_t i_bcnt_lo; /* low 32-bits of 40-bit */
809 volatile uint32_t reserved4:24;
810 volatile uint32_t a_bcnt_hi:8;/* high 8-bits of 40-bit "Average" */
811 volatile uint32_t a_bcnt_lo; /* low 32-bits of 40-bit */
812 volatile uint32_t lgt; /* Last Group Tick */
813 volatile uint8_t reserved5[12];
816 volatile uint8_t reserved[30];
819 volatile uint32_t __state[8];
824 volatile uint16_t channel_wq; /* ignores wq (3 lsbits) */
826 volatile uint16_t id:13; /* enum qm_channel */
827 volatile uint16_t reserved:3;
830 volatile uint8_t reserved[28];
831 volatile uint32_t wq_len[8];
885 * QM_MCR_QUERYCONGESTION(&res->querycongestion.state, cgr));
892 return (int)(p->__state[__CGR_WORD(cgr)] & (0x80000000 >> __CGR_SHIFT(cgr))); in QM_MCR_QUERYCONGESTION()
905 * always succeeds, but returns non-zero if there were "leaked" FQID
915 /* Managed (aka "shared" or "mux/demux") portal, high-level i/face */
919 /* ----------------- */
920 /* This wrapper represents a bit-array for the state of the 256 Qman congestion
933 return QM_MCR_QUERYCONGESTION(&c->q, (uint8_t)num); in QMAN_CGRS_GET()
937 c->q.__state[__CGR_WORD(num)] |= (0x80000000 >> __CGR_SHIFT(num)); in QMAN_CGRS_SET()
941 c->q.__state[__CGR_WORD(num)] &= ~(0x80000000 >> __CGR_SHIFT(num)); in QMAN_CGRS_UNSET()
945 /* ----------------------- */
960 /* Like _consume, but requests parking - FQ must be held-active */
962 /* Does not consume, for DCA mode only. This allows out-of-order
986 qman_cb_mr fqs; /* frame-queue state changes*/
999 #define QMAN_PORTAL_FLAG_IRQ_FAST 0x00000002 /* ... for fast-path too! */
1000 #define QMAN_PORTAL_FLAG_IRQ_SLOW 0x00000003 /* ... for slow-path too! */
1002 #define QMAN_PORTAL_FLAG_LOCKED 0x00000008 /* multi-core locking */
1003 #define QMAN_PORTAL_FLAG_NOTAFFINE 0x00000010 /* not cpu-default portal */
1015 #define QMAN_FQ_FLAG_LOCKED 0x00000008 /* multi-core locking */
1028 #define QMAN_FQ_STATE_VDQCR 0x08000000 /* being volatile dequeued */
1041 * hardware, bit-wise. */
1047 #define QMAN_ENQUEUE_FLAG_DCA 0x00008000 /* perform enqueue-DCA */
1055 /* For the ORP-specific qman_enqueue_orp() variant, this flag indicates "Not
1056 * Last In Sequence", ie. a non-terminating fragment. */
1058 /* - this flag performs no enqueue but fills in an ORP sequence number that
1061 /* - this flag performs no enqueue but advances NESN to the given sequence
1066 /* ------------- */
1068 * qman_free_fq - Deallocates a FQ
1070 * @flags: bit-mask of QMAN_FQ_FREE_*** options
1074 * FQ must be in the 'out-of-service' state unless the QMAN_FQ_FREE_PARKED flag
1080 * qman_fq_fqid - Queries the frame queue ID of a FQ object
1086 * qman_fq_state - Queries the state of a FQ object