Lines Matching +full:0 +full:x4001
63 default: bitMask = 0;break;}
90 #define PHY_MDIO_ADDR 0
93 #define PHY_SGMII_CR_PHY_RESET 0x8000
94 #define PHY_SGMII_CR_RESET_AN 0x0200
95 #define PHY_SGMII_CR_DEF_VAL 0x1140
96 #define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
97 #define PHY_SGMII_DEV_ABILITY_1000X 0x01A0
98 #define PHY_SGMII_IF_SPEED_GIGABIT 0x0008
99 #define PHY_SGMII_IF_MODE_AN 0x0002
100 #define PHY_SGMII_IF_MODE_SGMII 0x0001
101 #define PHY_SGMII_IF_MODE_1000X 0x0000
104 #define MEMAC_TO_MII_OFFSET 0x030 /* Offset from the MEM map to the MDIO mem map */