37 void fman_dtsec_stop_rx(struct dtsec_regs *regs)  in fman_dtsec_stop_rx()  argument
40 	iowrite32be(ioread32be(&regs->rctrl) | RCTRL_GRS, &regs->rctrl);  in fman_dtsec_stop_rx()
43 void fman_dtsec_stop_tx(struct dtsec_regs *regs)  in fman_dtsec_stop_tx()  argument
46 	iowrite32be(ioread32be(&regs->tctrl) | DTSEC_TCTRL_GTS, &regs->tctrl);  in fman_dtsec_stop_tx()
49 void fman_dtsec_start_tx(struct dtsec_regs *regs)  in fman_dtsec_start_tx()  argument
52 	iowrite32be(ioread32be(&regs->tctrl) & ~DTSEC_TCTRL_GTS, &regs->tctrl);  in fman_dtsec_start_tx()
55 void fman_dtsec_start_rx(struct dtsec_regs *regs)  in fman_dtsec_start_rx()  argument
58 	iowrite32be(ioread32be(&regs->rctrl) & ~RCTRL_GRS, &regs->rctrl);  in fman_dtsec_start_rx()
102 int fman_dtsec_init(struct dtsec_regs *regs, struct dtsec_cfg *cfg,  in fman_dtsec_init()  argument
119 	iowrite32be(MACCFG1_SOFT_RESET, &regs->maccfg1);  in fman_dtsec_init()
120 	iowrite32be(0, &regs->maccfg1);  in fman_dtsec_init()
123 	tmp =  ioread32be(&regs->tsec_id2);  in fman_dtsec_init()
155 	iowrite32be(tmp, &regs->ecntrl);  in fman_dtsec_init()
165 	iowrite32be(tmp, &regs->tctrl);  in fman_dtsec_init()
181 	iowrite32be(tmp, &regs->ptv);  in fman_dtsec_init()
199 	iowrite32be(tmp, &regs->rctrl);  in fman_dtsec_init()
207 	iowrite32be(cfg->tbipa, &regs->tbipa);  in fman_dtsec_init()
210 	iowrite32be(0, &regs->tmr_ctrl);  in fman_dtsec_init()
215 		iowrite32be(tmp, &regs->tmr_pevent);  in fman_dtsec_init()
220 			iowrite32be(tmp, &regs->tmr_pemask);  in fman_dtsec_init()
232 	iowrite32be(tmp, &regs->maccfg1);  in fman_dtsec_init()
259 	iowrite32be(tmp, &regs->maccfg2);  in fman_dtsec_init()
274 	iowrite32be(tmp, &regs->ipgifg);  in fman_dtsec_init()
295 	iowrite32be(tmp, &regs->hafdup);  in fman_dtsec_init()
300 	iowrite32be(cfg->maximum_frame, &regs->maxfrm);  in fman_dtsec_init()
305 	iowrite32be(0xffffffff, &regs->cam1);  in fman_dtsec_init()
306 	iowrite32be(0xffffffff, &regs->cam2);  in fman_dtsec_init()
309 	iowrite32be(exception_mask, &regs->imask);  in fman_dtsec_init()
313 	iowrite32be(0xffffffff, &regs->ievent);  in fman_dtsec_init()
321 	iowrite32be(tmp, &regs->macstnaddr1);  in fman_dtsec_init()
325 	iowrite32be(tmp, &regs->macstnaddr2);  in fman_dtsec_init()
332 		iowrite32be(0, &regs->igaddr[i]);  in fman_dtsec_init()
334 		iowrite32be(0, &regs->gaddr[i]);  in fman_dtsec_init()
337 	fman_dtsec_reset_stat(regs);  in fman_dtsec_init()
342 uint16_t fman_dtsec_get_max_frame_len(struct dtsec_regs *regs)  in fman_dtsec_get_max_frame_len()  argument
344 	return (uint16_t)ioread32be(&regs->maxfrm);  in fman_dtsec_get_max_frame_len()
347 void fman_dtsec_set_max_frame_len(struct dtsec_regs *regs, uint16_t length)  in fman_dtsec_set_max_frame_len()  argument
349 	iowrite32be(length, &regs->maxfrm);  in fman_dtsec_set_max_frame_len()
352 void fman_dtsec_set_mac_address(struct dtsec_regs *regs, uint8_t *adr)  in fman_dtsec_set_mac_address()  argument
360 	iowrite32be(tmp, &regs->macstnaddr1);  in fman_dtsec_set_mac_address()
364 	iowrite32be(tmp, &regs->macstnaddr2);  in fman_dtsec_set_mac_address()
367 void fman_dtsec_get_mac_address(struct dtsec_regs *regs, uint8_t *macaddr)  in fman_dtsec_get_mac_address()  argument
371 	tmp1 = ioread32be(&regs->macstnaddr1);  in fman_dtsec_get_mac_address()
372 	tmp2 = ioread32be(&regs->macstnaddr2);  in fman_dtsec_get_mac_address()
382 void fman_dtsec_set_hash_table(struct dtsec_regs *regs, uint32_t crc, bool mcast, bool ghtx)  in fman_dtsec_set_hash_table()  argument
393     fman_dtsec_set_bucket(regs, bucket, TRUE);  in fman_dtsec_set_hash_table()
396 void fman_dtsec_set_bucket(struct dtsec_regs *regs, int bucket, bool enable)  in fman_dtsec_set_bucket()  argument
404 		reg = &regs->gaddr[reg_idx-8];  in fman_dtsec_set_bucket()
406 		reg = &regs->igaddr[reg_idx];  in fman_dtsec_set_bucket()
414 void fman_dtsec_reset_filter_table(struct dtsec_regs *regs, bool mcast, bool ucast)  in fman_dtsec_reset_filter_table()  argument
419 	ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? TRUE : FALSE);  in fman_dtsec_reset_filter_table()
423 			iowrite32be(0, &regs->igaddr[i]);  in fman_dtsec_reset_filter_table()
427 			iowrite32be(0, &regs->gaddr[i]);  in fman_dtsec_reset_filter_table()
431 int fman_dtsec_set_tbi_phy_addr(struct dtsec_regs *regs,  in fman_dtsec_set_tbi_phy_addr()  argument
435 		iowrite32be(addr, &regs->tbipa);  in fman_dtsec_set_tbi_phy_addr()
442 void fman_dtsec_set_wol(struct dtsec_regs *regs, bool en)  in fman_dtsec_set_wol()  argument
446 	tmp = ioread32be(&regs->maccfg2);  in fman_dtsec_set_wol()
451 	iowrite32be(tmp, &regs->maccfg2);  in fman_dtsec_set_wol()
454 int fman_dtsec_adjust_link(struct dtsec_regs *regs,  in fman_dtsec_adjust_link()  argument
465 	tmp = ioread32be(&regs->maccfg2);  in fman_dtsec_adjust_link()
476 	iowrite32be(tmp, &regs->maccfg2);  in fman_dtsec_adjust_link()
478 	tmp = ioread32be(&regs->ecntrl);  in fman_dtsec_adjust_link()
483 	iowrite32be(tmp, &regs->ecntrl);  in fman_dtsec_adjust_link()
488 void fman_dtsec_set_uc_promisc(struct dtsec_regs *regs, bool enable)  in fman_dtsec_set_uc_promisc()  argument
492 	tmp = ioread32be(&regs->rctrl);  in fman_dtsec_set_uc_promisc()
499 	iowrite32be(tmp, &regs->rctrl);  in fman_dtsec_set_uc_promisc()
502 void fman_dtsec_set_mc_promisc(struct dtsec_regs *regs, bool enable)  in fman_dtsec_set_mc_promisc()  argument
506 	tmp = ioread32be(&regs->rctrl);  in fman_dtsec_set_mc_promisc()
513 	iowrite32be(tmp, &regs->rctrl);  in fman_dtsec_set_mc_promisc()
516 bool fman_dtsec_get_clear_carry_regs(struct dtsec_regs *regs,  in fman_dtsec_get_clear_carry_regs()  argument
520 	*car1 = ioread32be(&regs->car1);  in fman_dtsec_get_clear_carry_regs()
521 	*car2 = ioread32be(&regs->car2);  in fman_dtsec_get_clear_carry_regs()
524 		iowrite32be(*car1, &regs->car1);  in fman_dtsec_get_clear_carry_regs()
526 		iowrite32be(*car2, &regs->car2);  in fman_dtsec_get_clear_carry_regs()
531 void fman_dtsec_reset_stat(struct dtsec_regs *regs)  in fman_dtsec_reset_stat()  argument
534 	iowrite32be(ioread32be(&regs->ecntrl) |  in fman_dtsec_reset_stat()
535 			DTSEC_ECNTRL_CLRCNT, &regs->ecntrl);  in fman_dtsec_reset_stat()
538 int fman_dtsec_set_stat_level(struct dtsec_regs *regs, enum dtsec_stat_level level)  in fman_dtsec_set_stat_level()  argument
542 		iowrite32be(0xffffffff, &regs->cam1);  in fman_dtsec_set_stat_level()
543 		iowrite32be(0xffffffff, &regs->cam2);  in fman_dtsec_set_stat_level()
544 		iowrite32be(ioread32be(&regs->ecntrl) & ~DTSEC_ECNTRL_STEN,  in fman_dtsec_set_stat_level()
545 				&regs->ecntrl);  in fman_dtsec_set_stat_level()
546 		iowrite32be(ioread32be(&regs->imask) & ~DTSEC_IMASK_MSROEN,  in fman_dtsec_set_stat_level()
547 				&regs->imask);  in fman_dtsec_set_stat_level()
550 		iowrite32be(CAM1_ERRORS_ONLY, &regs->cam1);  in fman_dtsec_set_stat_level()
551 		iowrite32be(CAM2_ERRORS_ONLY, &regs->cam2);  in fman_dtsec_set_stat_level()
552 		iowrite32be(ioread32be(&regs->ecntrl) | DTSEC_ECNTRL_STEN,  in fman_dtsec_set_stat_level()
553 				&regs->ecntrl);  in fman_dtsec_set_stat_level()
554 		iowrite32be(ioread32be(&regs->imask) | DTSEC_IMASK_MSROEN,  in fman_dtsec_set_stat_level()
555 				&regs->imask);  in fman_dtsec_set_stat_level()
558 		iowrite32be((uint32_t)~CAM1_MIB_GRP_1, &regs->cam1);  in fman_dtsec_set_stat_level()
559 		iowrite32be((uint32_t)~CAM2_MIB_GRP_1, &regs->cam2);  in fman_dtsec_set_stat_level()
560 		iowrite32be(ioread32be(&regs->ecntrl) | DTSEC_ECNTRL_STEN,  in fman_dtsec_set_stat_level()
561 				&regs->ecntrl);  in fman_dtsec_set_stat_level()
562 		iowrite32be(ioread32be(&regs->imask) | DTSEC_IMASK_MSROEN,  in fman_dtsec_set_stat_level()
563 				&regs->imask);  in fman_dtsec_set_stat_level()
566 		iowrite32be(0, &regs->cam1);  in fman_dtsec_set_stat_level()
567 		iowrite32be(0, &regs->cam2);  in fman_dtsec_set_stat_level()
568 		iowrite32be(ioread32be(&regs->ecntrl) | DTSEC_ECNTRL_STEN,  in fman_dtsec_set_stat_level()
569 				&regs->ecntrl);  in fman_dtsec_set_stat_level()
570 		iowrite32be(ioread32be(&regs->imask) | DTSEC_IMASK_MSROEN,  in fman_dtsec_set_stat_level()
571 				&regs->imask);  in fman_dtsec_set_stat_level()
580 void fman_dtsec_set_ts(struct dtsec_regs *regs, bool en)  in fman_dtsec_set_ts()  argument
583 		iowrite32be(ioread32be(&regs->rctrl) | RCTRL_RTSE,  in fman_dtsec_set_ts()
584 				&regs->rctrl);  in fman_dtsec_set_ts()
585 		iowrite32be(ioread32be(&regs->tctrl) | DTSEC_TCTRL_TTSE,  in fman_dtsec_set_ts()
586 				&regs->tctrl);  in fman_dtsec_set_ts()
588 		iowrite32be(ioread32be(&regs->rctrl) & ~RCTRL_RTSE,  in fman_dtsec_set_ts()
589 				&regs->rctrl);  in fman_dtsec_set_ts()
590 		iowrite32be(ioread32be(&regs->tctrl) & ~DTSEC_TCTRL_TTSE,  in fman_dtsec_set_ts()
591 				&regs->tctrl);  in fman_dtsec_set_ts()
595 void fman_dtsec_enable(struct dtsec_regs *regs, bool apply_rx, bool apply_tx)  in fman_dtsec_enable()  argument
599 	tmp = ioread32be(&regs->maccfg1);  in fman_dtsec_enable()
607 	iowrite32be(tmp, &regs->maccfg1);  in fman_dtsec_enable()
610 void fman_dtsec_clear_addr_in_paddr(struct dtsec_regs *regs, uint8_t paddr_num)  in fman_dtsec_clear_addr_in_paddr()  argument
612     iowrite32be(0, &regs->macaddr[paddr_num].exact_match1);  in fman_dtsec_clear_addr_in_paddr()
613     iowrite32be(0, &regs->macaddr[paddr_num].exact_match2);  in fman_dtsec_clear_addr_in_paddr()
616 void fman_dtsec_add_addr_in_paddr(struct dtsec_regs *regs,  in fman_dtsec_add_addr_in_paddr()  argument
628 	iowrite32be(tmp, &regs->macaddr[paddr_num].exact_match1);  in fman_dtsec_add_addr_in_paddr()
636 	iowrite32be(tmp, &regs->macaddr[paddr_num].exact_match2);  in fman_dtsec_add_addr_in_paddr()
639 void fman_dtsec_disable(struct dtsec_regs *regs, bool apply_rx, bool apply_tx)  in fman_dtsec_disable()  argument
643 	tmp = ioread32be(&regs->maccfg1);  in fman_dtsec_disable()
651 	iowrite32be(tmp, &regs->maccfg1);  in fman_dtsec_disable()
654 void fman_dtsec_set_tx_pause_frames(struct dtsec_regs *regs, uint16_t time)  in fman_dtsec_set_tx_pause_frames()  argument
661 		ptv = ioread32be(&regs->ptv);  in fman_dtsec_set_tx_pause_frames()
664 		iowrite32be(ptv, &regs->ptv);  in fman_dtsec_set_tx_pause_frames()
667 		iowrite32be(ioread32be(&regs->maccfg1) | MACCFG1_TX_FLOW,  in fman_dtsec_set_tx_pause_frames()
668 				&regs->maccfg1);  in fman_dtsec_set_tx_pause_frames()
670 		iowrite32be(ioread32be(&regs->maccfg1) & ~MACCFG1_TX_FLOW,  in fman_dtsec_set_tx_pause_frames()
671 				&regs->maccfg1);  in fman_dtsec_set_tx_pause_frames()
674 void fman_dtsec_handle_rx_pause(struct dtsec_regs *regs, bool en)  in fman_dtsec_handle_rx_pause()  argument
680 	tmp = ioread32be(&regs->maccfg1);  in fman_dtsec_handle_rx_pause()
685 	iowrite32be(tmp, &regs->maccfg1);  in fman_dtsec_handle_rx_pause()
688 uint32_t fman_dtsec_get_rctrl(struct dtsec_regs *regs)  in fman_dtsec_get_rctrl()  argument
690 	return ioread32be(&regs->rctrl);  in fman_dtsec_get_rctrl()
693 uint32_t fman_dtsec_get_revision(struct dtsec_regs *regs)  in fman_dtsec_get_revision()  argument
695 	return ioread32be(&regs->tsec_id);  in fman_dtsec_get_revision()
698 uint32_t fman_dtsec_get_event(struct dtsec_regs *regs, uint32_t ev_mask)  in fman_dtsec_get_event()  argument
700 	return ioread32be(&regs->ievent) & ev_mask;  in fman_dtsec_get_event()
703 void fman_dtsec_ack_event(struct dtsec_regs *regs, uint32_t ev_mask)  in fman_dtsec_ack_event()  argument
705 	iowrite32be(ev_mask, &regs->ievent);  in fman_dtsec_ack_event()
708 uint32_t fman_dtsec_get_interrupt_mask(struct dtsec_regs *regs)  in fman_dtsec_get_interrupt_mask()  argument
710 	return ioread32be(&regs->imask);  in fman_dtsec_get_interrupt_mask()
713 uint32_t fman_dtsec_check_and_clear_tmr_event(struct dtsec_regs *regs)  in fman_dtsec_check_and_clear_tmr_event()  argument
717 	event = ioread32be(&regs->tmr_pevent);  in fman_dtsec_check_and_clear_tmr_event()
718 	event &= ioread32be(&regs->tmr_pemask);  in fman_dtsec_check_and_clear_tmr_event()
721 		iowrite32be(event, &regs->tmr_pevent);  in fman_dtsec_check_and_clear_tmr_event()
725 void fman_dtsec_enable_tmr_interrupt(struct dtsec_regs *regs)  in fman_dtsec_enable_tmr_interrupt()  argument
727 	iowrite32be(ioread32be(&regs->tmr_pemask) | TMR_PEMASK_TSREEN,  in fman_dtsec_enable_tmr_interrupt()
728 			&regs->tmr_pemask);  in fman_dtsec_enable_tmr_interrupt()
731 void fman_dtsec_disable_tmr_interrupt(struct dtsec_regs *regs)  in fman_dtsec_disable_tmr_interrupt()  argument
733 	iowrite32be(ioread32be(&regs->tmr_pemask) & ~TMR_PEMASK_TSREEN,  in fman_dtsec_disable_tmr_interrupt()
734 			&regs->tmr_pemask);  in fman_dtsec_disable_tmr_interrupt()
737 void fman_dtsec_enable_interrupt(struct dtsec_regs *regs, uint32_t ev_mask)  in fman_dtsec_enable_interrupt()  argument
739 	iowrite32be(ioread32be(&regs->imask) | ev_mask, &regs->imask);  in fman_dtsec_enable_interrupt()
742 void fman_dtsec_disable_interrupt(struct dtsec_regs *regs, uint32_t ev_mask)  in fman_dtsec_disable_interrupt()  argument
744 	iowrite32be(ioread32be(&regs->imask) & ~ev_mask, &regs->imask);  in fman_dtsec_disable_interrupt()
747 uint32_t fman_dtsec_get_stat_counter(struct dtsec_regs *regs,  in fman_dtsec_get_stat_counter()  argument
754 		ret_val = ioread32be(&regs->tr64);  in fman_dtsec_get_stat_counter()
757 		ret_val = ioread32be(&regs->tr127);  in fman_dtsec_get_stat_counter()
760 		ret_val = ioread32be(&regs->tr255);  in fman_dtsec_get_stat_counter()
763 		ret_val = ioread32be(&regs->tr511);  in fman_dtsec_get_stat_counter()
766 		ret_val = ioread32be(&regs->tr1k);  in fman_dtsec_get_stat_counter()
769 		ret_val = ioread32be(&regs->trmax);  in fman_dtsec_get_stat_counter()
772 		ret_val = ioread32be(&regs->trmgv);  in fman_dtsec_get_stat_counter()
775 		ret_val = ioread32be(&regs->rbyt);  in fman_dtsec_get_stat_counter()
778 		ret_val = ioread32be(&regs->rpkt);  in fman_dtsec_get_stat_counter()
781 		ret_val = ioread32be(&regs->rmca);  in fman_dtsec_get_stat_counter()
784 		ret_val = ioread32be(&regs->rbca);  in fman_dtsec_get_stat_counter()
787 		ret_val = ioread32be(&regs->rxpf);  in fman_dtsec_get_stat_counter()
790 		ret_val = ioread32be(&regs->raln);  in fman_dtsec_get_stat_counter()
793 		ret_val = ioread32be(&regs->rflr);  in fman_dtsec_get_stat_counter()
796 		ret_val = ioread32be(&regs->rcde);  in fman_dtsec_get_stat_counter()
799 		ret_val = ioread32be(&regs->rcse);  in fman_dtsec_get_stat_counter()
802 		ret_val = ioread32be(&regs->rund);  in fman_dtsec_get_stat_counter()
805 		ret_val = ioread32be(&regs->rovr);  in fman_dtsec_get_stat_counter()
808 		ret_val = ioread32be(&regs->rfrg);  in fman_dtsec_get_stat_counter()
811 		ret_val = ioread32be(&regs->rjbr);  in fman_dtsec_get_stat_counter()
814 		ret_val = ioread32be(&regs->rdrp);  in fman_dtsec_get_stat_counter()
817 		ret_val = ioread32be(&regs->tfcs);  in fman_dtsec_get_stat_counter()
820 		ret_val = ioread32be(&regs->tbyt);  in fman_dtsec_get_stat_counter()
823 		ret_val = ioread32be(&regs->tpkt);  in fman_dtsec_get_stat_counter()
826 		ret_val = ioread32be(&regs->tmca);  in fman_dtsec_get_stat_counter()
829 		ret_val = ioread32be(&regs->tbca);  in fman_dtsec_get_stat_counter()
832 		ret_val = ioread32be(&regs->txpf);  in fman_dtsec_get_stat_counter()
835 		ret_val = ioread32be(&regs->tncl);  in fman_dtsec_get_stat_counter()
838 		ret_val = ioread32be(&regs->tdrp);  in fman_dtsec_get_stat_counter()