197 	ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);  in ena_com_admin_init_aenq()
198 	ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);  in ena_com_admin_init_aenq()
205 	ENA_REG_WRITE32(ena_dev->bus, aenq_caps, ena_dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);  in ena_com_admin_init_aenq()
902 		return ENA_REG_READ32(ena_dev->bus, ena_dev->reg_bar + offset);  in ena_com_reg_bar_read32()
914 			ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);  in ena_com_reg_bar_read32()
1358 	io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +  in ena_com_create_io_sq()
1501 	io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +  in ena_com_create_io_cq()
1506 			(u32 __iomem *)((uintptr_t)ena_dev->reg_bar +  in ena_com_create_io_cq()
1614 	ENA_REG_WRITE32(ena_dev->bus, depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);  in ena_com_admin_aenq_enable()
1784 			ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);  in ena_com_set_admin_polling_mode()
1978 	ENA_REG_WRITE32(ena_dev->bus, phc->req_id, ena_dev->reg_bar + phc->doorbell_offset);  in ena_com_phc_get_timestamp()
2087 	ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);  in ena_com_mmio_reg_read_request_destroy()
2088 	ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);  in ena_com_mmio_reg_read_request_destroy()
2108 	ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);  in ena_com_mmio_reg_read_request_write_dev_addr()
2109 	ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);  in ena_com_mmio_reg_read_request_write_dev_addr()
2154 	admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +  in ena_com_admin_init()
2160 	ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);  in ena_com_admin_init()
2161 	ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);  in ena_com_admin_init()
2166 	ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);  in ena_com_admin_init()
2167 	ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);  in ena_com_admin_init()
2181 	ENA_REG_WRITE32(ena_dev->bus, aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);  in ena_com_admin_init()
2182 	ENA_REG_WRITE32(ena_dev->bus, acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);  in ena_com_admin_init()
2502 				ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);  in ena_com_aenq_intr_handler()
2618 	ENA_REG_WRITE32(ena_dev->bus, reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);  in ena_com_dev_reset()
2631 	ENA_REG_WRITE32(ena_dev->bus, 0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);  in ena_com_dev_reset()