Lines Matching +full:bus +full:- +full:width

4   PCI Root Bridge I/O protocol is used by PCI Bus Driver to perform PCI Memory, PCI I/O,
6   defferent types of bus mastering DMA.
8   Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
9   SPDX-License-Identifier: BSD-2-Clause-Patent
53   /// A read operation from system memory by a bus master that is not capable of producing
58   /// A write operation from system memory by a bus master that is not capable of producing
63   /// Provides both read and write access to system memory by both the processor and a bus
68   /// A read operation from system memory by a bus master that is capable of producing PCI
73   /// A write operation to system memory by a bus master that is capable of producing PCI
78   /// Provides both read and write access to system memory by both the processor and a bus
104 #define EFI_PCI_ADDRESS(bus, dev, func, reg) \  argument
106   (((UINTN) bus) << 24) | \
115   UINT8     Bus;  member
124   @param  Width                 Signifies the width of the memory or I/O operations.
141   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH    Width,
153   @param  Width                 Signifies the width of the memory operations.
168   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH    Width,
190   @param  Width                 Signifies the width of the memory operations.
196   @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
204   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH    Width,
211   Provides the PCI controller-specific addresses required to access system memory from a
212   DMA bus master.
215 …@param  Operation             Indicates if the bus master is going to read or write to system memo…
219 …@param  DeviceAddress         The resulting map address for the bus master PCI controller to use to