Lines Matching +full:bus +full:- +full:range
5 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
49 #define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit de…
50 #define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater…
52 #define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit …
53 #define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x…
54 #define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F…
55 #define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x37…
56 #define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 ///< Map a memory range so writes are co…
60 #define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 ///< Map a memory range so all r/w acces…
61 #define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 ///< Disable a memory range
62 #define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device
65 #define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 ///< I/O cycles 0x0100-0x03FF or greater…
67 #define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x40000 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x…
79 /// A read operation from system memory by a bus master.
83 /// A write operation from system memory by a bus master.
88 …/// bus master. The buffer is coherent from both the processor's and the bus master's point of vie…
172 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
212 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
259 @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count
261 @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is
280 Provides the PCI controller-specific addresses needed to access system memory.
283 …@param Operation Indicates if the bus master is going to read or write to system memo…
287 …@param DeviceAddress The resulting map address for the bus master PCI controller to use to
291 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
315 @retval EFI_SUCCESS The range was unmapped.
336 allocated range.
337 @param Attributes The requested bit mask of attributes for the allocated range.
362 @param HostAddress The base system memory address of the allocated range.
365 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
395 Retrieves this PCI controller's current PCI bus number, device number, and function number.
399 @param BusNumber The PCI controller's current PCI bus number.
451 … base address for resource range. The legal range for this field is 0..5.
476 Sets the attributes for a range of a BAR on a PCI controller.
479 @param Attributes The mask of attributes to set for the resource range specified by
482 … base address for resource range. The legal range for this field is 0..5.
483 …@param Offset A pointer to the BAR relative base address of the resource range to …
485 @param Length A pointer to the length of the resource range to be modified by the
489 range specified by BarIndex, Offset, and Length were
490 set on the PCI controller, and the actual resource range is returned
495 resource range specified by BarIndex, Offset, and
512 /// There is one EFI_PCI_IO_PROTOCOL instance for each PCI controller on a PCI bus.
539 /// A pointer to the in memory copy of the ROM image. The PCI Bus Driver is responsible
542 /// through the ROM BAR of the PCI controller, or it is from a platform-specific location.