Lines Matching +full:write +full:- +full:only

5   is used by a PCI root bridge I/O driver to perform memory-mapped I/O and I/O transactions.
7   bus-specific configuration cycles, such as the transitional configuration address and data
8   ports for PCI. Only drivers that require direct access to the entire system should use this
11   Note: This is a boot-services only protocol and it may not be used by runtime drivers after
15   Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
16   SPDX-License-Identifier: BSD-2-Clause-Patent
56   The Io.Read() and Io.Write() functions enable a driver to access PCI controller
70   EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
72   write operation is performed Count times on the same Address.
75   EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
77   write operation is performed Count times from the first element of Buffer.
85                             For write operations, the source buffer from which to write data.
106 /// Service for read and write accesses.
114   /// This service provides the various modalities of memory and I/O write.
116   EFI_CPU_IO_PROTOCOL_IO_MEM    Write;  member
125   /// Enables a driver to access memory-mapped registers in the EFI system memory space.