Lines Matching +full:apb +full:- +full:intc
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
9 #include <dt-bindings/power/thead,th1520-power.h>
10 #include <dt-bindings/reset/thead,th1520-reset.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
20 timebase-frequency = <3000000>;
26 riscv,isa-base = "rv64i";
27 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
30 i-cache-block-size = <64>;
31 i-cache-size = <65536>;
32 i-cache-sets = <512>;
33 d-cache-block-size = <64>;
34 d-cache-size = <65536>;
35 d-cache-sets = <512>;
36 next-level-cache = <&l2_cache>;
37 mmu-type = "riscv,sv39";
39 cpu0_intc: interrupt-controller {
40 compatible = "riscv,cpu-intc";
41 interrupt-controller;
42 #interrupt-cells = <1>;
50 riscv,isa-base = "rv64i";
51 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
54 i-cache-block-size = <64>;
55 i-cache-size = <65536>;
56 i-cache-sets = <512>;
57 d-cache-block-size = <64>;
58 d-cache-size = <65536>;
59 d-cache-sets = <512>;
60 next-level-cache = <&l2_cache>;
61 mmu-type = "riscv,sv39";
63 cpu1_intc: interrupt-controller {
64 compatible = "riscv,cpu-intc";
65 interrupt-controller;
66 #interrupt-cells = <1>;
74 riscv,isa-base = "rv64i";
75 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
78 i-cache-block-size = <64>;
79 i-cache-size = <65536>;
80 i-cache-sets = <512>;
81 d-cache-block-size = <64>;
82 d-cache-size = <65536>;
83 d-cache-sets = <512>;
84 next-level-cache = <&l2_cache>;
85 mmu-type = "riscv,sv39";
87 cpu2_intc: interrupt-controller {
88 compatible = "riscv,cpu-intc";
89 interrupt-controller;
90 #interrupt-cells = <1>;
98 riscv,isa-base = "rv64i";
99 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
102 i-cache-block-size = <64>;
103 i-cache-size = <65536>;
104 i-cache-sets = <512>;
105 d-cache-block-size = <64>;
106 d-cache-size = <65536>;
107 d-cache-sets = <512>;
108 next-level-cache = <&l2_cache>;
109 mmu-type = "riscv,sv39";
111 cpu3_intc: interrupt-controller {
112 compatible = "riscv,cpu-intc";
113 interrupt-controller;
114 #interrupt-cells = <1>;
118 l2_cache: l2-cache {
120 cache-block-size = <64>;
121 cache-level = <2>;
122 cache-size = <1048576>;
123 cache-sets = <1024>;
124 cache-unified;
130 riscv,event-to-mhpmcounters =
147 riscv,event-to-mhpmevent =
164 riscv,raw-event-to-mhpmcounters =
210 compatible = "fixed-clock";
211 clock-output-names = "osc_24m";
212 #clock-cells = <0>;
215 osc_32k: 32k-oscillator {
216 compatible = "fixed-clock";
217 clock-output-names = "osc_32k";
218 #clock-cells = <0>;
221 aonsys_clk: clock-73728000 {
222 compatible = "fixed-clock";
223 clock-frequency = <73728000>;
224 clock-output-names = "aonsys_clk";
225 #clock-cells = <0>;
228 stmmac_axi_config: stmmac-axi-config {
235 compatible = "thead,th1520-aon";
237 mbox-names = "aon";
239 reset-names = "gpu-clkgen";
240 #power-domain-cells = <1>;
244 compatible = "simple-bus";
245 interrupt-parent = <&plic>;
246 #address-cells = <2>;
247 #size-cells = <2>;
248 dma-noncoherent;
251 plic: interrupt-controller@ffd8000000 {
252 compatible = "thead,th1520-plic", "thead,c900-plic";
254 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
258 interrupt-controller;
259 #address-cells = <0>;
260 #interrupt-cells = <2>;
265 compatible = "thead,th1520-clint", "thead,c900-clint";
267 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
274 compatible = "thead,th1520-spi", "snps,dw-apb-ssi";
278 #address-cells = <1>;
279 #size-cells = <0>;
284 compatible = "snps,dw-apb-uart";
288 clock-names = "baudclk", "apb_pclk";
289 reg-shift = <2>;
290 reg-io-width = <4>;
295 compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
297 reg-names = "dwmac", "apb";
299 interrupt-names = "macirq";
302 clock-names = "stmmaceth", "pclk", "apb";
304 snps,fixed-burst;
305 snps,multicast-filter-bins = <64>;
306 snps,perfect-filter-entries = <32>;
307 snps,axi-config = <&stmmac_axi_config>;
311 compatible = "snps,dwmac-mdio";
312 #address-cells = <1>;
313 #size-cells = <0>;
318 compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
320 reg-names = "dwmac", "apb";
322 interrupt-names = "macirq";
325 clock-names = "stmmaceth", "pclk", "apb";
327 snps,fixed-burst;
328 snps,multicast-filter-bins = <64>;
329 snps,perfect-filter-entries = <32>;
330 snps,axi-config = <&stmmac_axi_config>;
334 compatible = "snps,dwmac-mdio";
335 #address-cells = <1>;
336 #size-cells = <0>;
341 compatible = "thead,th1520-dwcmshc";
345 clock-names = "core";
350 compatible = "thead,th1520-dwcmshc";
354 clock-names = "core";
359 compatible = "thead,th1520-dwcmshc";
363 clock-names = "core";
368 compatible = "snps,dw-apb-uart";
372 clock-names = "baudclk", "apb_pclk";
373 reg-shift = <2>;
374 reg-io-width = <4>;
379 compatible = "snps,dw-apb-uart";
383 clock-names = "baudclk", "apb_pclk";
384 reg-shift = <2>;
385 reg-io-width = <4>;
390 compatible = "snps,dw-apb-gpio";
392 #address-cells = <1>;
393 #size-cells = <0>;
395 clock-names = "bus";
397 gpio2: gpio-controller@0 {
398 compatible = "snps,dw-apb-gpio-port";
399 gpio-controller;
400 #gpio-cells = <2>;
402 gpio-ranges = <&padctrl0_apsys 0 0 32>;
404 interrupt-controller;
405 #interrupt-cells = <2>;
411 compatible = "snps,dw-apb-gpio";
413 #address-cells = <1>;
414 #size-cells = <0>;
416 clock-names = "bus";
418 gpio3: gpio-controller@0 {
419 compatible = "snps,dw-apb-gpio-port";
420 gpio-controller;
421 #gpio-cells = <2>;
423 gpio-ranges = <&padctrl0_apsys 0 32 23>;
425 interrupt-controller;
426 #interrupt-cells = <2>;
432 compatible = "thead,th1520-pinctrl";
435 thead,pad-group = <2>;
439 compatible = "snps,dw-apb-gpio";
441 #address-cells = <1>;
442 #size-cells = <0>;
444 clock-names = "bus";
446 gpio0: gpio-controller@0 {
447 compatible = "snps,dw-apb-gpio-port";
448 gpio-controller;
449 #gpio-cells = <2>;
451 gpio-ranges = <&padctrl1_apsys 0 0 32>;
453 interrupt-controller;
454 #interrupt-cells = <2>;
460 compatible = "snps,dw-apb-gpio";
462 #address-cells = <1>;
463 #size-cells = <0>;
465 clock-names = "bus";
467 gpio1: gpio-controller@0 {
468 compatible = "snps,dw-apb-gpio-port";
469 gpio-controller;
470 #gpio-cells = <2>;
472 gpio-ranges = <&padctrl1_apsys 0 32 31>;
474 interrupt-controller;
475 #interrupt-cells = <2>;
481 compatible = "thead,th1520-pinctrl";
484 thead,pad-group = <3>;
488 compatible = "snps,dw-apb-uart";
492 clock-names = "baudclk", "apb_pclk";
493 reg-shift = <2>;
494 reg-io-width = <4>;
498 clk: clock-controller@ffef010000 {
499 compatible = "thead,th1520-clk-ap";
502 #clock-cells = <1>;
505 rst: reset-controller@ffef528000 {
506 compatible = "thead,th1520-reset";
508 #reset-cells = <1>;
511 clk_vo: clock-controller@ffef528050 {
512 compatible = "thead,th1520-clk-vo";
515 #clock-cells = <1>;
518 dmac0: dma-controller@ffefc00000 {
519 compatible = "snps,axi-dma-1.01a";
523 clock-names = "core-clk", "cfgr-clk";
524 #dma-cells = <1>;
525 dma-channels = <4>;
526 snps,block-size = <65536 65536 65536 65536>;
528 snps,dma-masters = <1>;
529 snps,data-width = <4>;
530 snps,axi-max-burst-len = <16>;
535 compatible = "snps,dw-apb-timer";
538 clock-names = "timer";
544 compatible = "snps,dw-apb-timer";
547 clock-names = "timer";
553 compatible = "snps,dw-apb-timer";
556 clock-names = "timer";
562 compatible = "snps,dw-apb-timer";
565 clock-names = "timer";
571 compatible = "snps,dw-apb-uart";
575 clock-names = "baudclk", "apb_pclk";
576 reg-shift = <2>;
577 reg-io-width = <4>;
582 compatible = "snps,dw-apb-uart";
586 clock-names = "baudclk", "apb_pclk";
587 reg-shift = <2>;
588 reg-io-width = <4>;
593 compatible = "snps,dw-apb-timer";
596 clock-names = "timer";
602 compatible = "snps,dw-apb-timer";
605 clock-names = "timer";
611 compatible = "snps,dw-apb-timer";
614 clock-names = "timer";
620 compatible = "snps,dw-apb-timer";
623 clock-names = "timer";
629 compatible = "thead,th1520-mbox";
634 reg-names = "local", "remote-icu0", "remote-icu1", "remote-icu2";
637 clock-names = "clk-local", "clk-remote-icu0", "clk-remote-icu1",
638 "clk-remote-icu2";
639 interrupt-parent = <&plic>;
641 #mbox-cells = <1>;
645 compatible = "snps,dw-apb-gpio";
647 #address-cells = <1>;
648 #size-cells = <0>;
650 aogpio: gpio-controller@0 {
651 compatible = "snps,dw-apb-gpio-port";
652 gpio-controller;
653 #gpio-cells = <2>;
655 gpio-ranges = <&padctrl_aosys 0 9 16>;
657 interrupt-controller;
658 #interrupt-cells = <2>;
664 compatible = "thead,th1520-pinctrl";
667 thead,pad-group = <1>;
676 reg-names = "common", "ts", "pd", "vm";
678 #thermal-sensor-cells = <1>;
682 compatible = "snps,dw-apb-gpio";
684 #address-cells = <1>;
685 #size-cells = <0>;
687 gpio4: gpio-controller@0 {
688 compatible = "snps,dw-apb-gpio-port";
689 gpio-controller;
690 #gpio-cells = <2>;
692 gpio-ranges = <&padctrl_aosys 0 25 22>, <&padctrl_aosys 22 7 1>;
694 interrupt-controller;
695 #interrupt-cells = <2>;