Lines Matching +full:2 +full:- +full:compatible
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "thead,th1520";
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 timebase-frequency = <3000000>;
20 compatible = "thead,c910", "riscv";
23 riscv,isa-base = "rv64i";
24 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
27 i-cache-block-size = <64>;
28 i-cache-size = <65536>;
29 i-cache-sets = <512>;
30 d-cache-block-size = <64>;
31 d-cache-size = <65536>;
32 d-cache-sets = <512>;
33 next-level-cache = <&l2_cache>;
34 mmu-type = "riscv,sv39";
36 cpu0_intc: interrupt-controller {
37 compatible = "riscv,cpu-intc";
38 interrupt-controller;
39 #interrupt-cells = <1>;
44 compatible = "thead,c910", "riscv";
47 riscv,isa-base = "rv64i";
48 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
51 i-cache-block-size = <64>;
52 i-cache-size = <65536>;
53 i-cache-sets = <512>;
54 d-cache-block-size = <64>;
55 d-cache-size = <65536>;
56 d-cache-sets = <512>;
57 next-level-cache = <&l2_cache>;
58 mmu-type = "riscv,sv39";
60 cpu1_intc: interrupt-controller {
61 compatible = "riscv,cpu-intc";
62 interrupt-controller;
63 #interrupt-cells = <1>;
67 c910_2: cpu@2 {
68 compatible = "thead,c910", "riscv";
71 riscv,isa-base = "rv64i";
72 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
74 reg = <2>;
75 i-cache-block-size = <64>;
76 i-cache-size = <65536>;
77 i-cache-sets = <512>;
78 d-cache-block-size = <64>;
79 d-cache-size = <65536>;
80 d-cache-sets = <512>;
81 next-level-cache = <&l2_cache>;
82 mmu-type = "riscv,sv39";
84 cpu2_intc: interrupt-controller {
85 compatible = "riscv,cpu-intc";
86 interrupt-controller;
87 #interrupt-cells = <1>;
92 compatible = "thead,c910", "riscv";
95 riscv,isa-base = "rv64i";
96 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
99 i-cache-block-size = <64>;
100 i-cache-size = <65536>;
101 i-cache-sets = <512>;
102 d-cache-block-size = <64>;
103 d-cache-size = <65536>;
104 d-cache-sets = <512>;
105 next-level-cache = <&l2_cache>;
106 mmu-type = "riscv,sv39";
108 cpu3_intc: interrupt-controller {
109 compatible = "riscv,cpu-intc";
110 interrupt-controller;
111 #interrupt-cells = <1>;
115 l2_cache: l2-cache {
116 compatible = "cache";
117 cache-block-size = <64>;
118 cache-level = <2>;
119 cache-size = <1048576>;
120 cache-sets = <1024>;
121 cache-unified;
126 compatible = "fixed-clock";
127 clock-output-names = "osc_24m";
128 #clock-cells = <0>;
131 osc_32k: 32k-oscillator {
132 compatible = "fixed-clock";
133 clock-output-names = "osc_32k";
134 #clock-cells = <0>;
137 apb_clk: apb-clk-clock {
138 compatible = "fixed-clock";
139 clock-output-names = "apb_clk";
140 #clock-cells = <0>;
143 uart_sclk: uart-sclk-clock {
144 compatible = "fixed-clock";
145 clock-output-names = "uart_sclk";
146 #clock-cells = <0>;
149 sdhci_clk: sdhci-clock {
150 compatible = "fixed-clock";
151 clock-frequency = <198000000>;
152 clock-output-names = "sdhci_clk";
153 #clock-cells = <0>;
157 compatible = "simple-bus";
158 interrupt-parent = <&plic>;
159 #address-cells = <2>;
160 #size-cells = <2>;
161 dma-noncoherent;
164 plic: interrupt-controller@ffd8000000 {
165 compatible = "thead,th1520-plic", "thead,c900-plic";
167 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
171 interrupt-controller;
172 #address-cells = <0>;
173 #interrupt-cells = <2>;
178 compatible = "thead,th1520-clint", "thead,c900-clint";
180 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
187 compatible = "snps,dw-apb-uart";
191 reg-shift = <2>;
192 reg-io-width = <4>;
197 compatible = "snps,dw-apb-uart";
201 reg-shift = <2>;
202 reg-io-width = <4>;
207 compatible = "snps,dw-apb-uart";
211 reg-shift = <2>;
212 reg-io-width = <4>;
217 compatible = "snps,dw-apb-gpio";
219 #address-cells = <1>;
220 #size-cells = <0>;
222 portc: gpio-controller@0 {
223 compatible = "snps,dw-apb-gpio-port";
224 gpio-controller;
225 #gpio-cells = <2>;
228 interrupt-controller;
229 #interrupt-cells = <2>;
235 compatible = "snps,dw-apb-gpio";
237 #address-cells = <1>;
238 #size-cells = <0>;
240 portd: gpio-controller@0 {
241 compatible = "snps,dw-apb-gpio-port";
242 gpio-controller;
243 #gpio-cells = <2>;
246 interrupt-controller;
247 #interrupt-cells = <2>;
253 compatible = "snps,dw-apb-gpio";
255 #address-cells = <1>;
256 #size-cells = <0>;
258 porta: gpio-controller@0 {
259 compatible = "snps,dw-apb-gpio-port";
260 gpio-controller;
261 #gpio-cells = <2>;
264 interrupt-controller;
265 #interrupt-cells = <2>;
271 compatible = "snps,dw-apb-gpio";
273 #address-cells = <1>;
274 #size-cells = <0>;
276 portb: gpio-controller@0 {
277 compatible = "snps,dw-apb-gpio-port";
278 gpio-controller;
279 #gpio-cells = <2>;
282 interrupt-controller;
283 #interrupt-cells = <2>;
289 compatible = "snps,dw-apb-uart";
293 reg-shift = <2>;
294 reg-io-width = <4>;
298 dmac0: dma-controller@ffefc00000 {
299 compatible = "snps,axi-dma-1.01a";
303 clock-names = "core-clk", "cfgr-clk";
304 #dma-cells = <1>;
305 dma-channels = <4>;
306 snps,block-size = <65536 65536 65536 65536>;
307 snps,priority = <0 1 2 3>;
308 snps,dma-masters = <1>;
309 snps,data-width = <4>;
310 snps,axi-max-burst-len = <16>;
315 compatible = "thead,th1520-dwcmshc";
319 clock-names = "core";
324 compatible = "thead,th1520-dwcmshc";
328 clock-names = "core";
333 compatible = "thead,th1520-dwcmshc";
337 clock-names = "core";
342 compatible = "snps,dw-apb-timer";
345 clock-names = "timer";
351 compatible = "snps,dw-apb-timer";
354 clock-names = "timer";
360 compatible = "snps,dw-apb-timer";
363 clock-names = "timer";
369 compatible = "snps,dw-apb-timer";
372 clock-names = "timer";
378 compatible = "snps,dw-apb-uart";
382 reg-shift = <2>;
383 reg-io-width = <4>;
388 compatible = "snps,dw-apb-uart";
392 reg-shift = <2>;
393 reg-io-width = <4>;
398 compatible = "snps,dw-apb-timer";
401 clock-names = "timer";
407 compatible = "snps,dw-apb-timer";
410 clock-names = "timer";
416 compatible = "snps,dw-apb-timer";
419 clock-names = "timer";
425 compatible = "snps,dw-apb-timer";
428 clock-names = "timer";
434 compatible = "snps,dw-apb-gpio";
436 #address-cells = <1>;
437 #size-cells = <0>;
439 porte: gpio-controller@0 {
440 compatible = "snps,dw-apb-gpio-port";
441 gpio-controller;
442 #gpio-cells = <2>;
445 interrupt-controller;
446 #interrupt-cells = <2>;
452 compatible = "snps,dw-apb-gpio";
454 #address-cells = <1>;
455 #size-cells = <0>;
457 portf: gpio-controller@0 {
458 compatible = "snps,dw-apb-gpio-port";
459 gpio-controller;
460 #gpio-cells = <2>;
463 interrupt-controller;
464 #interrupt-cells = <2>;