Lines Matching +full:jh7110 +full:- +full:aoncrg
1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "starfive,jh7110";
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
26 i-cache-block-size = <64>;
27 i-cache-sets = <64>;
28 i-cache-size = <16384>;
29 next-level-cache = <&ccache>;
31 riscv,isa-base = "rv64i";
32 riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr",
36 cpu0_intc: interrupt-controller {
37 compatible = "riscv,cpu-intc";
38 interrupt-controller;
39 #interrupt-cells = <1>;
44 compatible = "sifive,u74-mc", "riscv";
46 d-cache-block-size = <64>;
47 d-cache-sets = <64>;
48 d-cache-size = <32768>;
49 d-tlb-sets = <1>;
50 d-tlb-size = <40>;
52 i-cache-block-size = <64>;
53 i-cache-sets = <64>;
54 i-cache-size = <32768>;
55 i-tlb-sets = <1>;
56 i-tlb-size = <40>;
57 mmu-type = "riscv,sv39";
58 next-level-cache = <&ccache>;
60 riscv,isa-base = "rv64i";
61 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
63 tlb-split;
64 operating-points-v2 = <&cpu_opp>;
66 clock-names = "cpu";
67 #cooling-cells = <2>;
69 cpu1_intc: interrupt-controller {
70 compatible = "riscv,cpu-intc";
71 interrupt-controller;
72 #interrupt-cells = <1>;
77 compatible = "sifive,u74-mc", "riscv";
79 d-cache-block-size = <64>;
80 d-cache-sets = <64>;
81 d-cache-size = <32768>;
82 d-tlb-sets = <1>;
83 d-tlb-size = <40>;
85 i-cache-block-size = <64>;
86 i-cache-sets = <64>;
87 i-cache-size = <32768>;
88 i-tlb-sets = <1>;
89 i-tlb-size = <40>;
90 mmu-type = "riscv,sv39";
91 next-level-cache = <&ccache>;
93 riscv,isa-base = "rv64i";
94 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
96 tlb-split;
97 operating-points-v2 = <&cpu_opp>;
99 clock-names = "cpu";
100 #cooling-cells = <2>;
102 cpu2_intc: interrupt-controller {
103 compatible = "riscv,cpu-intc";
104 interrupt-controller;
105 #interrupt-cells = <1>;
110 compatible = "sifive,u74-mc", "riscv";
112 d-cache-block-size = <64>;
113 d-cache-sets = <64>;
114 d-cache-size = <32768>;
115 d-tlb-sets = <1>;
116 d-tlb-size = <40>;
118 i-cache-block-size = <64>;
119 i-cache-sets = <64>;
120 i-cache-size = <32768>;
121 i-tlb-sets = <1>;
122 i-tlb-size = <40>;
123 mmu-type = "riscv,sv39";
124 next-level-cache = <&ccache>;
126 riscv,isa-base = "rv64i";
127 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
129 tlb-split;
130 operating-points-v2 = <&cpu_opp>;
132 clock-names = "cpu";
133 #cooling-cells = <2>;
135 cpu3_intc: interrupt-controller {
136 compatible = "riscv,cpu-intc";
137 interrupt-controller;
138 #interrupt-cells = <1>;
143 compatible = "sifive,u74-mc", "riscv";
145 d-cache-block-size = <64>;
146 d-cache-sets = <64>;
147 d-cache-size = <32768>;
148 d-tlb-sets = <1>;
149 d-tlb-size = <40>;
151 i-cache-block-size = <64>;
152 i-cache-sets = <64>;
153 i-cache-size = <32768>;
154 i-tlb-sets = <1>;
155 i-tlb-size = <40>;
156 mmu-type = "riscv,sv39";
157 next-level-cache = <&ccache>;
159 riscv,isa-base = "rv64i";
160 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
162 tlb-split;
163 operating-points-v2 = <&cpu_opp>;
165 clock-names = "cpu";
166 #cooling-cells = <2>;
168 cpu4_intc: interrupt-controller {
169 compatible = "riscv,cpu-intc";
170 interrupt-controller;
171 #interrupt-cells = <1>;
175 cpu-map {
200 cpu_opp: opp-table-0 {
201 compatible = "operating-points-v2";
202 opp-shared;
203 opp-375000000 {
204 opp-hz = /bits/ 64 <375000000>;
205 opp-microvolt = <800000>;
207 opp-500000000 {
208 opp-hz = /bits/ 64 <500000000>;
209 opp-microvolt = <800000>;
211 opp-750000000 {
212 opp-hz = /bits/ 64 <750000000>;
213 opp-microvolt = <800000>;
215 opp-1500000000 {
216 opp-hz = /bits/ 64 <1500000000>;
217 opp-microvolt = <1040000>;
221 thermal-zones {
222 cpu-thermal {
223 polling-delay-passive = <250>;
224 polling-delay = <15000>;
226 thermal-sensors = <&sfctemp>;
228 cooling-maps {
231 cooling-device =
240 cpu_alert0: cpu-alert0 {
247 cpu-crit {
257 dvp_clk: dvp-clock {
258 compatible = "fixed-clock";
259 clock-output-names = "dvp_clk";
260 #clock-cells = <0>;
262 gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
263 compatible = "fixed-clock";
264 clock-output-names = "gmac0_rgmii_rxin";
265 #clock-cells = <0>;
268 gmac0_rmii_refin: gmac0-rmii-refin-clock {
269 compatible = "fixed-clock";
270 clock-output-names = "gmac0_rmii_refin";
271 #clock-cells = <0>;
274 gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
275 compatible = "fixed-clock";
276 clock-output-names = "gmac1_rgmii_rxin";
277 #clock-cells = <0>;
280 gmac1_rmii_refin: gmac1-rmii-refin-clock {
281 compatible = "fixed-clock";
282 clock-output-names = "gmac1_rmii_refin";
283 #clock-cells = <0>;
286 hdmitx0_pixelclk: hdmitx0-pixel-clock {
287 compatible = "fixed-clock";
288 clock-output-names = "hdmitx0_pixelclk";
289 #clock-cells = <0>;
292 i2srx_bclk_ext: i2srx-bclk-ext-clock {
293 compatible = "fixed-clock";
294 clock-output-names = "i2srx_bclk_ext";
295 #clock-cells = <0>;
298 i2srx_lrck_ext: i2srx-lrck-ext-clock {
299 compatible = "fixed-clock";
300 clock-output-names = "i2srx_lrck_ext";
301 #clock-cells = <0>;
304 i2stx_bclk_ext: i2stx-bclk-ext-clock {
305 compatible = "fixed-clock";
306 clock-output-names = "i2stx_bclk_ext";
307 #clock-cells = <0>;
310 i2stx_lrck_ext: i2stx-lrck-ext-clock {
311 compatible = "fixed-clock";
312 clock-output-names = "i2stx_lrck_ext";
313 #clock-cells = <0>;
316 mclk_ext: mclk-ext-clock {
317 compatible = "fixed-clock";
318 clock-output-names = "mclk_ext";
319 #clock-cells = <0>;
323 compatible = "fixed-clock";
324 clock-output-names = "osc";
325 #clock-cells = <0>;
328 rtc_osc: rtc-oscillator {
329 compatible = "fixed-clock";
330 clock-output-names = "rtc_osc";
331 #clock-cells = <0>;
334 stmmac_axi_setup: stmmac-axi-config {
341 tdm_ext: tdm-ext-clock {
342 compatible = "fixed-clock";
343 clock-output-names = "tdm_ext";
344 #clock-cells = <0>;
348 compatible = "simple-bus";
349 interrupt-parent = <&plic>;
350 #address-cells = <2>;
351 #size-cells = <2>;
355 compatible = "starfive,jh7110-clint", "sifive,clint0";
357 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
364 ccache: cache-controller@2010000 {
365 compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
368 cache-block-size = <64>;
369 cache-level = <2>;
370 cache-sets = <2048>;
371 cache-size = <2097152>;
372 cache-unified;
375 plic: interrupt-controller@c000000 {
376 compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
378 interrupts-extended = <&cpu0_intc 11>,
383 interrupt-controller;
384 #interrupt-cells = <1>;
385 #address-cells = <0>;
390 compatible = "snps,dw-apb-uart";
394 clock-names = "baudclk", "apb_pclk";
397 reg-io-width = <4>;
398 reg-shift = <2>;
403 compatible = "snps,dw-apb-uart";
407 clock-names = "baudclk", "apb_pclk";
410 reg-io-width = <4>;
411 reg-shift = <2>;
416 compatible = "snps,dw-apb-uart";
420 clock-names = "baudclk", "apb_pclk";
423 reg-io-width = <4>;
424 reg-shift = <2>;
429 compatible = "snps,designware-i2c";
432 clock-names = "ref";
435 #address-cells = <1>;
436 #size-cells = <0>;
441 compatible = "snps,designware-i2c";
444 clock-names = "ref";
447 #address-cells = <1>;
448 #size-cells = <0>;
453 compatible = "snps,designware-i2c";
456 clock-names = "ref";
459 #address-cells = <1>;
460 #size-cells = <0>;
469 clock-names = "sspclk", "apb_pclk";
472 arm,primecell-periphid = <0x00041022>;
473 num-cs = <1>;
474 #address-cells = <1>;
475 #size-cells = <0>;
484 clock-names = "sspclk", "apb_pclk";
487 arm,primecell-periphid = <0x00041022>;
488 num-cs = <1>;
489 #address-cells = <1>;
490 #size-cells = <0>;
499 clock-names = "sspclk", "apb_pclk";
502 arm,primecell-periphid = <0x00041022>;
503 num-cs = <1>;
504 #address-cells = <1>;
505 #size-cells = <0>;
510 compatible = "starfive,jh7110-tdm";
518 clock-names = "tdm_ahb", "tdm_apb",
525 dma-names = "rx","tx";
526 #sound-dai-cells = <0>;
531 compatible = "starfive,jh7110-i2srx";
542 clock-names = "i2sclk", "apb", "mclk",
548 dma-names = "tx", "rx";
550 #sound-dai-cells = <0>;
555 compatible = "starfive,jh7110-pwmdac";
559 clock-names = "apb", "core";
562 dma-names = "tx";
563 #sound-dai-cells = <0>;
568 compatible = "starfive,jh7110-usb";
570 #address-cells = <1>;
571 #size-cells = <1>;
572 starfive,stg-syscon = <&stg_syscon 0x4>;
578 clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
583 reset-names = "pwrup", "apb", "axi", "utmi_apb";
591 reg-names = "otg", "xhci", "dev";
593 interrupt-names = "host", "peripheral", "otg";
595 phy-names = "cdns3,usb2-phy";
600 compatible = "starfive,jh7110-usb-phy";
604 clock-names = "125m", "app_125m";
605 #phy-cells = <0>;
609 compatible = "starfive,jh7110-pcie-phy";
611 #phy-cells = <0>;
615 compatible = "starfive,jh7110-pcie-phy";
617 #phy-cells = <0>;
620 stgcrg: clock-controller@10230000 {
621 compatible = "starfive,jh7110-stgcrg";
631 clock-names = "osc", "hifi4_core",
635 #clock-cells = <1>;
636 #reset-cells = <1>;
640 compatible = "starfive,jh7110-stg-syscon", "syscon";
645 compatible = "snps,dw-apb-uart";
649 clock-names = "baudclk", "apb_pclk";
652 reg-io-width = <4>;
653 reg-shift = <2>;
658 compatible = "snps,dw-apb-uart";
662 clock-names = "baudclk", "apb_pclk";
665 reg-io-width = <4>;
666 reg-shift = <2>;
671 compatible = "snps,dw-apb-uart";
675 clock-names = "baudclk", "apb_pclk";
678 reg-io-width = <4>;
679 reg-shift = <2>;
684 compatible = "snps,designware-i2c";
687 clock-names = "ref";
690 #address-cells = <1>;
691 #size-cells = <0>;
696 compatible = "snps,designware-i2c";
699 clock-names = "ref";
702 #address-cells = <1>;
703 #size-cells = <0>;
708 compatible = "snps,designware-i2c";
711 clock-names = "ref";
714 #address-cells = <1>;
715 #size-cells = <0>;
720 compatible = "snps,designware-i2c";
723 clock-names = "ref";
726 #address-cells = <1>;
727 #size-cells = <0>;
736 clock-names = "sspclk", "apb_pclk";
739 arm,primecell-periphid = <0x00041022>;
740 num-cs = <1>;
741 #address-cells = <1>;
742 #size-cells = <0>;
751 clock-names = "sspclk", "apb_pclk";
754 arm,primecell-periphid = <0x00041022>;
755 num-cs = <1>;
756 #address-cells = <1>;
757 #size-cells = <0>;
766 clock-names = "sspclk", "apb_pclk";
769 arm,primecell-periphid = <0x00041022>;
770 num-cs = <1>;
771 #address-cells = <1>;
772 #size-cells = <0>;
781 clock-names = "sspclk", "apb_pclk";
784 arm,primecell-periphid = <0x00041022>;
785 num-cs = <1>;
786 #address-cells = <1>;
787 #size-cells = <0>;
792 compatible = "starfive,jh7110-i2stx0";
799 clock-names = "i2sclk", "apb", "mclk",
804 dma-names = "tx";
805 #sound-dai-cells = <0>;
810 compatible = "starfive,jh7110-i2stx1";
821 clock-names = "i2sclk", "apb", "mclk",
827 dma-names = "tx";
828 #sound-dai-cells = <0>;
832 sfctemp: temperature-sensor@120e0000 {
833 compatible = "starfive,jh7110-temp";
837 clock-names = "sense", "bus";
840 reset-names = "sense", "bus";
841 #thermal-sensor-cells = <0>;
845 compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
852 clock-names = "ref", "ahb", "apb";
856 reset-names = "qspi", "qspi-ocp", "rstc_ref";
857 cdns,fifo-depth = <256>;
858 cdns,fifo-width = <4>;
859 cdns,trigger-address = <0x0>;
863 syscrg: clock-controller@13020000 {
864 compatible = "starfive,jh7110-syscrg";
874 clock-names = "osc", "gmac1_rmii_refin",
880 #clock-cells = <1>;
881 #reset-cells = <1>;
885 compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
888 pllclk: clock-controller {
889 compatible = "starfive,jh7110-pll";
891 #clock-cells = <1>;
896 compatible = "starfive,jh7110-sys-pinctrl";
901 interrupt-controller;
902 #interrupt-cells = <2>;
903 gpio-controller;
904 #gpio-cells = <2>;
908 compatible = "starfive,jh7110-wdt";
912 clock-names = "apb", "core";
918 compatible = "starfive,jh7110-crypto";
922 clock-names = "hclk", "ahb";
926 dma-names = "tx", "rx";
929 sdma: dma-controller@16008000 {
931 arm,primecell-periphid = <0x00041080>;
935 clock-names = "apb_pclk";
937 lli-bus-interface-ahb1;
938 mem-bus-interface-ahb1;
939 memcpy-burst-size = <256>;
940 memcpy-bus-width = <32>;
941 #dma-cells = <2>;
945 compatible = "starfive,jh7110-trng";
949 clock-names = "hclk", "ahb";
955 compatible = "starfive,jh7110-mmc";
959 clock-names = "biu","ciu";
961 reset-names = "reset";
963 fifo-depth = <32>;
964 fifo-watermark-aligned;
965 data-addr = <0>;
971 compatible = "starfive,jh7110-mmc";
975 clock-names = "biu","ciu";
977 reset-names = "reset";
979 fifo-depth = <32>;
980 fifo-watermark-aligned;
981 data-addr = <0>;
987 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
989 clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
990 <&aoncrg JH7110_AONCLK_GMAC0_AHB>,
992 <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
994 clock-names = "stmmaceth", "pclk", "ptp_ref",
996 resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
997 <&aoncrg JH7110_AONRST_GMAC0_AHB>;
998 reset-names = "stmmaceth", "ahb";
1000 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1001 rx-fifo-depth = <2048>;
1002 tx-fifo-depth = <2048>;
1003 snps,multicast-filter-bins = <64>;
1004 snps,perfect-filter-entries = <256>;
1005 snps,fixed-burst;
1006 snps,no-pbl-x8;
1008 snps,axi-config = <&stmmac_axi_setup>;
1010 snps,en-tx-lpi-clockgating;
1018 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
1025 clock-names = "stmmaceth", "pclk", "ptp_ref",
1029 reset-names = "stmmaceth", "ahb";
1031 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1032 rx-fifo-depth = <2048>;
1033 tx-fifo-depth = <2048>;
1034 snps,multicast-filter-bins = <64>;
1035 snps,perfect-filter-entries = <256>;
1036 snps,fixed-burst;
1037 snps,no-pbl-x8;
1039 snps,axi-config = <&stmmac_axi_setup>;
1041 snps,en-tx-lpi-clockgating;
1048 dma: dma-controller@16050000 {
1049 compatible = "starfive,jh7110-axi-dma";
1053 clock-names = "core-clk", "cfgr-clk";
1057 #dma-cells = <1>;
1058 dma-channels = <4>;
1059 snps,dma-masters = <1>;
1060 snps,data-width = <3>;
1061 snps,block-size = <65536 65536 65536 65536>;
1063 snps,axi-max-burst-len = <16>;
1066 aoncrg: clock-controller@17000000 {
1067 compatible = "starfive,jh7110-aoncrg";
1075 clock-names = "osc", "gmac0_rmii_refin",
1079 #clock-cells = <1>;
1080 #reset-cells = <1>;
1084 compatible = "starfive,jh7110-aon-syscon", "syscon";
1086 #power-domain-cells = <1>;
1090 compatible = "starfive,jh7110-aon-pinctrl";
1092 resets = <&aoncrg JH7110_AONRST_IOMUX>;
1094 interrupt-controller;
1095 #interrupt-cells = <2>;
1096 gpio-controller;
1097 #gpio-cells = <2>;
1100 pwrc: power-controller@17030000 {
1101 compatible = "starfive,jh7110-pmu";
1104 #power-domain-cells = <1>;
1107 ispcrg: clock-controller@19810000 {
1108 compatible = "starfive,jh7110-ispcrg";
1114 clock-names = "isp_top_core", "isp_top_axi",
1119 #clock-cells = <1>;
1120 #reset-cells = <1>;
1121 power-domains = <&pwrc JH7110_PD_ISP>;
1124 voutcrg: clock-controller@295c0000 {
1125 compatible = "starfive,jh7110-voutcrg";
1133 clock-names = "vout_src", "vout_top_ahb",
1137 #clock-cells = <1>;
1138 #reset-cells = <1>;
1139 power-domains = <&pwrc JH7110_PD_VOUT>;