Lines Matching +full:jh7100 +full:- +full:pinctrl
1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
12 compatible = "starfive,jh7100";
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
24 d-cache-sets = <64>;
25 d-cache-size = <32768>;
26 d-tlb-sets = <1>;
27 d-tlb-size = <32>;
29 i-cache-block-size = <64>;
30 i-cache-sets = <64>;
31 i-cache-size = <32768>;
32 i-tlb-sets = <1>;
33 i-tlb-size = <32>;
34 mmu-type = "riscv,sv39";
35 next-level-cache = <&ccache>;
37 riscv,isa-base = "rv64i";
38 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
40 tlb-split;
42 cpu0_intc: interrupt-controller {
43 compatible = "riscv,cpu-intc";
44 interrupt-controller;
45 #interrupt-cells = <1>;
50 compatible = "sifive,u74-mc", "riscv";
52 d-cache-block-size = <64>;
53 d-cache-sets = <64>;
54 d-cache-size = <32768>;
55 d-tlb-sets = <1>;
56 d-tlb-size = <32>;
58 i-cache-block-size = <64>;
59 i-cache-sets = <64>;
60 i-cache-size = <32768>;
61 i-tlb-sets = <1>;
62 i-tlb-size = <32>;
63 mmu-type = "riscv,sv39";
64 next-level-cache = <&ccache>;
66 riscv,isa-base = "rv64i";
67 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
69 tlb-split;
71 cpu1_intc: interrupt-controller {
72 compatible = "riscv,cpu-intc";
73 interrupt-controller;
74 #interrupt-cells = <1>;
78 cpu-map {
91 thermal-zones {
92 cpu-thermal {
93 polling-delay-passive = <250>;
94 polling-delay = <15000>;
96 thermal-sensors = <&sfctemp>;
99 cpu-alert0 {
106 cpu-crit {
116 osc_sys: osc-sys {
117 compatible = "fixed-clock";
118 #clock-cells = <0>;
120 clock-frequency = <0>;
123 osc_aud: osc-aud {
124 compatible = "fixed-clock";
125 #clock-cells = <0>;
127 clock-frequency = <0>;
130 gmac_rmii_ref: gmac-rmii-ref {
131 compatible = "fixed-clock";
132 #clock-cells = <0>;
134 clock-frequency = <0>;
137 gmac_gr_mii_rxclk: gmac-gr-mii-rxclk {
138 compatible = "fixed-clock";
139 #clock-cells = <0>;
141 clock-frequency = <0>;
145 compatible = "simple-bus";
146 interrupt-parent = <&plic>;
147 #address-cells = <2>;
148 #size-cells = <2>;
149 dma-noncoherent;
153 compatible = "starfive,jh7100-clint", "sifive,clint0";
155 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
159 ccache: cache-controller@2010000 {
160 compatible = "starfive,jh7100-ccache", "sifive,ccache0", "cache";
163 cache-block-size = <64>;
164 cache-level = <2>;
165 cache-sets = <2048>;
166 cache-size = <2097152>;
167 cache-unified;
170 plic: interrupt-controller@c000000 {
171 compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
173 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
175 interrupt-controller;
176 #address-cells = <0>;
177 #interrupt-cells = <1>;
182 compatible = "snps,dw-mshc";
186 clock-names = "biu", "ciu";
188 data-addr = <0>;
189 fifo-depth = <32>;
190 fifo-watermark-aligned;
195 compatible = "snps,dw-mshc";
199 clock-names = "biu", "ciu";
201 data-addr = <0>;
202 fifo-depth = <32>;
203 fifo-watermark-aligned;
207 clkgen: clock-controller@11800000 {
208 compatible = "starfive,jh7100-clkgen";
211 clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";
212 #clock-cells = <1>;
215 rstgen: reset-controller@11840000 {
216 compatible = "starfive,jh7100-reset";
218 #reset-cells = <1>;
222 compatible = "snps,designware-i2c";
226 clock-names = "ref", "pclk";
229 #address-cells = <1>;
230 #size-cells = <0>;
235 compatible = "snps,designware-i2c";
239 clock-names = "ref", "pclk";
242 #address-cells = <1>;
243 #size-cells = <0>;
247 gpio: pinctrl@11910000 {
248 compatible = "starfive,jh7100-pinctrl";
251 reg-names = "gpio", "padctl";
255 gpio-controller;
256 #gpio-cells = <2>;
257 interrupt-controller;
258 #interrupt-cells = <2>;
262 compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
266 clock-names = "baudclk", "apb_pclk";
269 reg-io-width = <4>;
270 reg-shift = <2>;
275 compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
279 clock-names = "baudclk", "apb_pclk";
282 reg-io-width = <4>;
283 reg-shift = <2>;
288 compatible = "snps,designware-i2c";
292 clock-names = "ref", "pclk";
295 #address-cells = <1>;
296 #size-cells = <0>;
301 compatible = "snps,designware-i2c";
305 clock-names = "ref", "pclk";
308 #address-cells = <1>;
309 #size-cells = <0>;
314 compatible = "starfive,jh7100-wdt";
318 clock-names = "apb", "core";
323 sfctemp: temperature-sensor@124a0000 {
324 compatible = "starfive,jh7100-temp";
328 clock-names = "sense", "bus";
331 reset-names = "sense", "bus";
332 #thermal-sensor-cells = <0>;