Lines Matching +full:plic +full:- +full:1
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
30 i-cache-size = <16384>;
33 riscv,isa-base = "rv64i";
34 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
37 cpu0_intc: interrupt-controller {
38 #interrupt-cells = <1>;
39 compatible = "riscv,cpu-intc";
40 interrupt-controller;
43 cpu1: cpu@1 {
44 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
45 d-cache-block-size = <64>;
46 d-cache-sets = <64>;
47 d-cache-size = <32768>;
48 d-tlb-sets = <1>;
49 d-tlb-size = <32>;
51 i-cache-block-size = <64>;
52 i-cache-sets = <64>;
53 i-cache-size = <32768>;
54 i-tlb-sets = <1>;
55 i-tlb-size = <32>;
56 mmu-type = "riscv,sv39";
57 reg = <1>;
59 riscv,isa-base = "rv64i";
60 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
62 tlb-split;
63 next-level-cache = <&l2cache>;
64 cpu1_intc: interrupt-controller {
65 #interrupt-cells = <1>;
66 compatible = "riscv,cpu-intc";
67 interrupt-controller;
71 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
72 d-cache-block-size = <64>;
73 d-cache-sets = <64>;
74 d-cache-size = <32768>;
75 d-tlb-sets = <1>;
76 d-tlb-size = <32>;
78 i-cache-block-size = <64>;
79 i-cache-sets = <64>;
80 i-cache-size = <32768>;
81 i-tlb-sets = <1>;
82 i-tlb-size = <32>;
83 mmu-type = "riscv,sv39";
86 riscv,isa-base = "rv64i";
87 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
89 tlb-split;
90 next-level-cache = <&l2cache>;
91 cpu2_intc: interrupt-controller {
92 #interrupt-cells = <1>;
93 compatible = "riscv,cpu-intc";
94 interrupt-controller;
98 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
99 d-cache-block-size = <64>;
100 d-cache-sets = <64>;
101 d-cache-size = <32768>;
102 d-tlb-sets = <1>;
103 d-tlb-size = <32>;
105 i-cache-block-size = <64>;
106 i-cache-sets = <64>;
107 i-cache-size = <32768>;
108 i-tlb-sets = <1>;
109 i-tlb-size = <32>;
110 mmu-type = "riscv,sv39";
113 riscv,isa-base = "rv64i";
114 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
116 tlb-split;
117 next-level-cache = <&l2cache>;
118 cpu3_intc: interrupt-controller {
119 #interrupt-cells = <1>;
120 compatible = "riscv,cpu-intc";
121 interrupt-controller;
125 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
126 d-cache-block-size = <64>;
127 d-cache-sets = <64>;
128 d-cache-size = <32768>;
129 d-tlb-sets = <1>;
130 d-tlb-size = <32>;
132 i-cache-block-size = <64>;
133 i-cache-sets = <64>;
134 i-cache-size = <32768>;
135 i-tlb-sets = <1>;
136 i-tlb-size = <32>;
137 mmu-type = "riscv,sv39";
140 riscv,isa-base = "rv64i";
141 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
143 tlb-split;
144 next-level-cache = <&l2cache>;
145 cpu4_intc: interrupt-controller {
146 #interrupt-cells = <1>;
147 compatible = "riscv,cpu-intc";
148 interrupt-controller;
152 cpu-map {
177 #address-cells = <2>;
178 #size-cells = <2>;
179 compatible = "simple-bus";
181 plic0: interrupt-controller@c000000 {
182 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
184 #address-cells = <0>;
185 #interrupt-cells = <1>;
186 interrupt-controller;
187 interrupts-extended =
195 prci: clock-controller@10000000 {
196 compatible = "sifive,fu540-c000-prci";
199 #clock-cells = <1>;
202 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
204 interrupt-parent = <&plic0>;
209 dma: dma-controller@3000000 {
210 compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
212 interrupt-parent = <&plic0>;
215 dma-channels = <4>;
216 #dma-cells = <1>;
219 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
221 interrupt-parent = <&plic0>;
227 compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
229 interrupt-parent = <&plic0>;
232 reg-shift = <2>;
233 reg-io-width = <1>;
234 #address-cells = <1>;
235 #size-cells = <0>;
239 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
242 interrupt-parent = <&plic0>;
245 #address-cells = <1>;
246 #size-cells = <0>;
250 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
253 interrupt-parent = <&plic0>;
256 #address-cells = <1>;
257 #size-cells = <0>;
261 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
263 interrupt-parent = <&plic0>;
266 #address-cells = <1>;
267 #size-cells = <0>;
271 compatible = "sifive,fu540-c000-gem";
272 interrupt-parent = <&plic0>;
276 local-mac-address = [00 00 00 00 00 00];
277 clock-names = "pclk", "hclk";
280 #address-cells = <1>;
281 #size-cells = <0>;
285 compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
287 interrupt-parent = <&plic0>;
290 #pwm-cells = <3>;
294 compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
296 interrupt-parent = <&plic0>;
299 #pwm-cells = <3>;
302 l2cache: cache-controller@2010000 {
303 compatible = "sifive,fu540-c000-ccache", "cache";
304 cache-block-size = <64>;
305 cache-level = <2>;
306 cache-sets = <1024>;
307 cache-size = <2097152>;
308 cache-unified;
309 interrupt-parent = <&plic0>;
310 interrupts = <1>, <2>, <3>;
314 compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
315 interrupt-parent = <&plic0>;
320 gpio-controller;
321 #gpio-cells = <2>;
322 interrupt-controller;
323 #interrupt-cells = <2>;