Lines Matching +full:plic +full:- +full:1
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <12000000>;
23 #cooling-cells = <2>;
27 riscv,isa-base = "rv64i";
28 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
31 mmu-type = "riscv,sv39";
32 i-cache-size = <0x8000>;
33 i-cache-line-size = <0x40>;
34 d-cache-size = <0x8000>;
35 d-cache-line-size = <0x40>;
36 next-level-cache = <&l2cache>;
38 operating-points-v2 = <&cluster0_opp>;
40 cpu0_intc: interrupt-controller {
41 #interrupt-cells = <1>;
42 compatible = "riscv,cpu-intc";
43 interrupt-controller;
50 dma-noncoherent;
51 interrupt-parent = <&plic>;
53 plic: interrupt-controller@12c00000 {
54 compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
55 #interrupt-cells = <2>;
56 #address-cells = <0>;
58 interrupt-controller;
61 power-domains = <&cpg>;
63 interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
66 l2cache: cache-controller@13400000 {
67 compatible = "andestech,ax45mp-cache", "cache";
70 cache-size = <0x40000>;
71 cache-line-size = <64>;
72 cache-sets = <1024>;
73 cache-unified;
74 cache-level = <2>;