Lines Matching +full:plic +full:- +full:1
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
5 compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
9 compatible = "microchip,corepwm-rtl-v4";
11 microchip,sync-update-mask = /bits/ 32 <0>;
12 #pwm-cells = <3>;
18 compatible = "microchip,corei2c-rtl-v7";
20 #address-cells = <1>;
21 #size-cells = <0>;
23 interrupt-parent = <&plic>;
25 clock-frequency = <100000>;
30 compatible = "microchip,pcie-host-1.0";
31 #address-cells = <0x3>;
32 #interrupt-cells = <0x1>;
33 #size-cells = <0x2>;
36 reg-names = "cfg", "apb";
37 bus-range = <0x0 0x7f>;
38 interrupt-parent = <&plic>;
40 interrupt-map = <0 0 0 1 &pcie_intc 0>,
41 <0 0 0 2 &pcie_intc 1>,
44 interrupt-map-mask = <0 0 0 7>;
46 clock-names = "fic1", "fic3";
48 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
49 msi-parent = <&pcie>;
50 msi-controller;
52 pcie_intc: interrupt-controller {
53 #address-cells = <0>;
54 #interrupt-cells = <1>;
55 interrupt-controller;
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
68 clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",