Lines Matching +full:plic +full:- +full:1
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
6 #include "microchip-mpfs-fabric.dtsi"
9 #address-cells = <2>;
10 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
21 i-cache-block-size = <64>;
22 i-cache-sets = <128>;
23 i-cache-size = <16384>;
29 cpu0_intc: interrupt-controller {
30 #interrupt-cells = <1>;
31 compatible = "riscv,cpu-intc";
32 interrupt-controller;
36 cpu1: cpu@1 {
37 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
38 d-cache-block-size = <64>;
39 d-cache-sets = <64>;
40 d-cache-size = <32768>;
41 d-tlb-sets = <1>;
42 d-tlb-size = <32>;
44 i-cache-block-size = <64>;
45 i-cache-sets = <64>;
46 i-cache-size = <32768>;
47 i-tlb-sets = <1>;
48 i-tlb-size = <32>;
49 mmu-type = "riscv,sv39";
50 reg = <1>;
53 tlb-split;
56 cpu1_intc: interrupt-controller {
57 #interrupt-cells = <1>;
58 compatible = "riscv,cpu-intc";
59 interrupt-controller;
64 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
65 d-cache-block-size = <64>;
66 d-cache-sets = <64>;
67 d-cache-size = <32768>;
68 d-tlb-sets = <1>;
69 d-tlb-size = <32>;
71 i-cache-block-size = <64>;
72 i-cache-sets = <64>;
73 i-cache-size = <32768>;
74 i-tlb-sets = <1>;
75 i-tlb-size = <32>;
76 mmu-type = "riscv,sv39";
80 tlb-split;
83 cpu2_intc: interrupt-controller {
84 #interrupt-cells = <1>;
85 compatible = "riscv,cpu-intc";
86 interrupt-controller;
91 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
92 d-cache-block-size = <64>;
93 d-cache-sets = <64>;
94 d-cache-size = <32768>;
95 d-tlb-sets = <1>;
96 d-tlb-size = <32>;
98 i-cache-block-size = <64>;
99 i-cache-sets = <64>;
100 i-cache-size = <32768>;
101 i-tlb-sets = <1>;
102 i-tlb-size = <32>;
103 mmu-type = "riscv,sv39";
107 tlb-split;
110 cpu3_intc: interrupt-controller {
111 #interrupt-cells = <1>;
112 compatible = "riscv,cpu-intc";
113 interrupt-controller;
118 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
119 d-cache-block-size = <64>;
120 d-cache-sets = <64>;
121 d-cache-size = <32768>;
122 d-tlb-sets = <1>;
123 d-tlb-size = <32>;
125 i-cache-block-size = <64>;
126 i-cache-sets = <64>;
127 i-cache-size = <32768>;
128 i-tlb-sets = <1>;
129 i-tlb-size = <32>;
130 mmu-type = "riscv,sv39";
134 tlb-split;
136 cpu4_intc: interrupt-controller {
137 #interrupt-cells = <1>;
138 compatible = "riscv,cpu-intc";
139 interrupt-controller;
145 compatible = "fixed-clock";
146 #clock-cells = <0>;
150 #address-cells = <2>;
151 #size-cells = <2>;
152 compatible = "simple-bus";
155 cctrllr: cache-controller@2010000 {
156 compatible = "sifive,fu540-c000-ccache", "cache";
158 cache-block-size = <64>;
159 cache-level = <2>;
160 cache-sets = <1024>;
161 cache-size = <2097152>;
162 cache-unified;
163 interrupt-parent = <&plic>;
164 interrupts = <1>, <2>, <3>;
168 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
170 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
177 plic: interrupt-controller@c000000 { label
178 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
180 #address-cells = <0>;
181 #interrupt-cells = <1>;
182 interrupt-controller;
183 interrupts-extended = <&cpu0_intc 11>,
192 compatible = "microchip,mpfs-clkcfg";
195 #clock-cells = <1>;
201 reg-io-width = <4>;
202 reg-shift = <2>;
203 interrupt-parent = <&plic>;
205 current-speed = <115200>;
213 reg-io-width = <4>;
214 reg-shift = <2>;
215 interrupt-parent = <&plic>;
217 current-speed = <115200>;
225 reg-io-width = <4>;
226 reg-shift = <2>;
227 interrupt-parent = <&plic>;
229 current-speed = <115200>;
237 reg-io-width = <4>;
238 reg-shift = <2>;
239 interrupt-parent = <&plic>;
241 current-speed = <115200>;
249 reg-io-width = <4>;
250 reg-shift = <2>;
251 interrupt-parent = <&plic>;
254 current-speed = <115200>;
260 compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
262 interrupt-parent = <&plic>;
265 max-frequency = <200000000>;
270 compatible = "microchip,mpfs-spi";
271 #address-cells = <1>;
272 #size-cells = <0>;
274 interrupt-parent = <&plic>;
277 spi-max-frequency = <25000000>;
282 compatible = "microchip,mpfs-spi";
283 #address-cells = <1>;
284 #size-cells = <0>;
286 interrupt-parent = <&plic>;
289 spi-max-frequency = <25000000>;
294 compatible = "microchip,mpfs-qspi";
295 #address-cells = <1>;
296 #size-cells = <0>;
298 interrupt-parent = <&plic>;
301 spi-max-frequency = <25000000>;
306 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
308 #address-cells = <1>;
309 #size-cells = <0>;
310 interrupt-parent = <&plic>;
313 clock-frequency = <100000>;
318 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
320 #address-cells = <1>;
321 #size-cells = <0>;
322 interrupt-parent = <&plic>;
325 clock-frequency = <100000>;
332 #address-cells = <1>;
333 #size-cells = <0>;
334 interrupt-parent = <&plic>;
336 local-mac-address = [00 00 00 00 00 00];
338 clock-names = "pclk", "hclk";
345 #address-cells = <1>;
346 #size-cells = <0>;
347 interrupt-parent = <&plic>;
349 local-mac-address = [00 00 00 00 00 00];
351 clock-names = "pclk", "hclk";
356 compatible = "microchip,mpfs-gpio";
358 interrupt-parent = <&plic>;
359 interrupt-controller;
360 #interrupt-cells = <1>;
362 gpio-controller;
363 #gpio-cells = <2>;
368 compatible = "microchip,mpfs-gpio";
370 interrupt-parent = <&plic>;
371 interrupt-controller;
372 #interrupt-cells = <1>;
374 gpio-controller;
375 #gpio-cells = <2>;
380 compatible = "microchip,mpfs-gpio";
382 interrupt-parent = <&plic>;
383 interrupt-controller;
384 #interrupt-cells = <1>;
386 gpio-controller;
387 #gpio-cells = <2>;
392 compatible = "microchip,mpfs-rtc";
394 interrupt-parent = <&plic>;
397 clock-names = "rtc", "rtcref";
402 compatible = "microchip,mpfs-musb";
404 interrupt-parent = <&plic>;
407 interrupt-names = "dma","mc";
412 compatible = "microchip,pcie-host-1.0";
413 #address-cells = <0x3>;
414 #interrupt-cells = <0x1>;
415 #size-cells = <0x2>;
418 reg-names = "cfg", "apb";
419 bus-range = <0x0 0x7f>;
420 interrupt-parent = <&plic>;
422 interrupt-map = <0 0 0 1 &pcie_intc 0>,
423 <0 0 0 2 &pcie_intc 1>,
426 interrupt-map-mask = <0 0 0 7>;
428 clock-names = "fic0", "fic1", "fic3";
430 msi-parent = <&pcie>;
431 msi-controller;
432 microchip,axi-m-atr0 = <0x10 0x0>;
434 pcie_intc: legacy-interrupt-controller {
435 #address-cells = <0>;
436 #interrupt-cells = <1>;
437 interrupt-controller;
442 compatible = "microchip,mpfs-mailbox";
444 interrupt-parent = <&plic>;
446 #mbox-cells = <1>;
451 compatible = "microchip,mpfs-sys-controller";