Lines Matching +full:soc +full:- +full:gpio10
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
7 * The Nezha-D1 has a 40-pin IO header. Some of these pins are routed
8 * directly to pads on the SoC, others come from an 8-bit pcf857x IO
12 * Lines which are routed to the 40-pin header are named as follows:
15 * <pin#> is the actual pin number of the 40-pin header
20 * http://dl.linux-sunxi.org/D1/D1_Nezha_development_board_schematic_diagram_20210224.pdf
23 #include <dt-bindings/gpio/gpio.h>
24 #include <dt-bindings/input/input.h>
26 /dts-v1/;
28 #include "sun20i-d1.dtsi"
29 #include "sun20i-common-regulators.dtsi"
33 compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1";
42 stdout-path = "serial0:115200n8";
46 compatible = "regulator-fixed";
47 regulator-name = "usbvbus";
48 regulator-min-microvolt = <5000000>;
49 regulator-max-microvolt = <5000000>;
51 enable-active-high;
52 vin-supply = <®_vcc>;
56 * This regulator is PWM-controlled, but the PWM controller is not
59 reg_vdd_cpu: vdd-cpu {
60 compatible = "regulator-fixed";
61 regulator-name = "vdd-cpu";
62 regulator-min-microvolt = <1100000>;
63 regulator-max-microvolt = <1100000>;
64 vin-supply = <®_vcc>;
67 wifi_pwrseq: wifi-pwrseq {
68 compatible = "mmc-pwrseq-simple";
69 reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
74 cpu-supply = <®_vdd_cpu>;
78 clock-frequency = <24000000>;
90 pinctrl-0 = <&rgmii_pe_pins>;
91 pinctrl-names = "default";
92 phy-handle = <&ext_rgmii_phy>;
93 phy-mode = "rgmii-id";
94 phy-supply = <®_vcc_3v3>;
99 pinctrl-0 = <&i2c2_pb0_pins>;
100 pinctrl-names = "default";
106 interrupt-parent = <&pio>;
108 interrupt-controller;
109 gpio-controller;
110 #gpio-cells = <2>;
111 #interrupt-cells = <2>;
112 gpio-line-names =
114 "pin16 [gpio10]",
125 ext_rgmii_phy: ethernet-phy@1 {
126 compatible = "ethernet-phy-ieee802.3-c22";
132 bus-width = <4>;
133 cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
134 disable-wp;
135 vmmc-supply = <®_vcc_3v3>;
136 vqmmc-supply = <®_vcc_3v3>;
137 pinctrl-0 = <&mmc0_pins>;
138 pinctrl-names = "default";
143 bus-width = <4>;
144 mmc-pwrseq = <&wifi_pwrseq>;
145 non-removable;
146 vmmc-supply = <®_vcc_3v3>;
147 vqmmc-supply = <®_vcc_3v3>;
148 pinctrl-0 = <&mmc1_pins>;
149 pinctrl-names = "default";
154 interrupt-parent = <&pio>;
156 interrupt-names = "host-wake";
169 pinctrl-0 = <&uart0_pb8_pins>;
170 pinctrl-names = "default";
175 uart-has-rtscts;
176 pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
177 pinctrl-names = "default";
189 usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
190 usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
191 usb0_vbus-supply = <®_usbvbus>;
192 usb1_vbus-supply = <®_vcc>;
197 gpio-line-names =
204 "pin5 [gpio2/twi2-sck]",
205 "pin3 [gpio1/twi2-sda]",
207 "pin38 [gpio24/i2s2-din]",
208 "pin40 [gpio25/i2s2-dout]",
209 "pin12 [gpio7/i2s-clk]",
210 "pin35 [gpio22/i2s2-lrck]",
212 "pin8 [gpio4/uart0-txd]",
213 "pin10 [gpio5/uart0-rxd]",
230 "pin24 [gpio16/spi1-ce0]",
231 "pin23 [gpio15/spi1-clk]",
232 "pin19 [gpio12/spi1-mosi]",
233 "pin21 [gpio13/spi1-miso]",
234 "pin27 [gpio18/spi1-hold]",
235 "pin29 [gpio20/spi1-wp]",