Lines Matching +full:0 +full:xc300
27 #size-cells = <0>;
29 PowerPC,8572@0 {
31 reg = <0x0>;
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
44 reg = <0x1>;
47 d-cache-size = <0x8000>; // L1, 32K
48 i-cache-size = <0x8000>; // L1, 32K
49 timebase-frequency = <0>;
50 bus-frequency = <0>;
51 clock-frequency = <0>;
58 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
65 reg = <0 0xef005000 0 0x1000>;
69 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
70 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
71 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
72 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
74 nor-boot@0,0 {
77 reg = <0 0 0x8000000>; /* 128MB */
80 partition@0 {
82 reg = <0x00000000 0x6f00000>; /* 111 MB */
86 reg = <0x6f00000 0x1000000>; /* 16 MB */
90 reg = <0x7f00000 0x40000>; /* 256 KB */
94 reg = <0x7f40000 0x40000>; /* 256 KB */
98 reg = <0x7f80000 0x80000>; /* 512 KB */
103 nor-alternate@1,0 {
106 //reg = <0xf0000000 0x08000000>; /* 128MB */
107 reg = <1 0 0x8000000>; /* 128MB */
110 partition@0 {
112 reg = <0x00000000 0x6f00000>; /* 111 MB */
116 reg = <0x6f00000 0x1000000>; /* 16 MB */
120 reg = <0x7f00000 0x40000>; /* 256 KB */
124 reg = <0x7f40000 0x40000>; /* 256 KB */
128 reg = <0x7f80000 0x80000>; /* 512 KB */
133 nand@2,0 {
144 reg = <2 0 0x40000>;
146 partition@0 {
148 reg = <0 0x40000000>;
159 ranges = <0x0 0 0xef000000 0x100000>;
160 bus-frequency = <0>; // Filled out by uboot.
162 ecm-law@0 {
164 reg = <0x0 0x1000>;
170 reg = <0x1000 0x1000>;
177 reg = <0x2000 0x1000>;
184 reg = <0x6000 0x1000>;
191 reg = <0x20000 0x1000>;
193 cache-size = <0x100000>; // L2, 1M
200 #size-cells = <0>;
201 cell-index = <0>;
203 reg = <0x3000 0x100>;
210 reg = <0x48>;
215 reg = <0x4c>;
220 reg = <0x51>;
225 reg = <0x54>;
231 reg = <0x68>;
236 reg = <0x70>;
241 reg = <0x18>;
244 polarity = <0x00>;
249 reg = <0x1c>;
252 polarity = <0x00>;
257 reg = <0x1e>;
260 polarity = <0x00>;
265 reg = <0x1f>;
268 polarity = <0x00>;
274 #size-cells = <0>;
277 reg = <0x3100 0x100>;
287 reg = <0xc300 0x4>;
288 ranges = <0x0 0xc100 0x200>;
290 dma-channel@0 {
293 reg = <0x0 0x80>;
294 cell-index = <0>;
301 reg = <0x80 0x80>;
309 reg = <0x100 0x80>;
317 reg = <0x180 0x80>;
328 reg = <0x21300 0x4>;
329 ranges = <0x0 0x21100 0x200>;
330 cell-index = <0>;
331 dma-channel@0 {
334 reg = <0x0 0x80>;
335 cell-index = <0>;
342 reg = <0x80 0x80>;
350 reg = <0x100 0x80>;
358 reg = <0x180 0x80>;
369 cell-index = <0>;
373 reg = <0x24000 0x1000>;
374 ranges = <0x0 0x24000 0x1000>;
384 #size-cells = <0>;
386 reg = <0x520 0x20>;
391 reg = <0x1>;
396 reg = <0x2>;
399 reg = <0x11>;
413 reg = <0x25000 0x1000>;
414 ranges = <0x0 0x25000 0x1000>;
424 #size-cells = <0>;
426 reg = <0x520 0x20>;
429 reg = <0x11>;
437 cell-index = <0>;
440 reg = <0x4500 0x100>;
441 clock-frequency = <0>;
451 reg = <0x4600 0x100>;
452 clock-frequency = <0>;
459 reg = <0xe0000 0x1000>;
465 reg = <0x41600 0x80>;
466 msi-available-ranges = <0 0x100>;
468 0xe0 0
469 0xe1 0
470 0xe2 0
471 0xe3 0
472 0xe4 0
473 0xe5 0
474 0xe6 0
475 0xe7 0>;
480 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
481 "fsl,sec2.1", "fsl,sec2.0";
482 reg = <0x30000 0x10000>;
487 fsl,exec-units-mask = <0x9fe>;
488 fsl,descriptor-types-mask = <0x3ab0ebf>;
493 #address-cells = <0>;
495 reg = <0x40000 0x40000>;
502 reg = <0xf000 0x1000>;
537 reg = <0x10000 0x5000>;
544 reg = <0x2f000 0x1000>;
551 reg = <0x15000 0x1000>;
569 reg = <0 0xef009000 0 0x1000>;
570 bus-range = <0 255>;
571 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
572 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>;
576 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
578 /* IDSEL 0x0 */
579 0x0 0x0 0x0 0x1 &mpic 0x4 0x1
580 0x0 0x0 0x0 0x2 &mpic 0x5 0x1
581 0x0 0x0 0x0 0x3 &mpic 0x6 0x1
582 0x0 0x0 0x0 0x4 &mpic 0x7 0x1
584 pcie@0 {
585 reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
589 ranges = <0x2000000 0x0 0xc0000000
590 0x2000000 0x0 0xc0000000
591 0x0 0x10000000
593 0x1000000 0x0 0x0
594 0x1000000 0x0 0x0
595 0x0 0x100000>;
606 reg = <0 0xef00a000 0 0x1000>;
607 bus-range = <0 255>;
608 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
609 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
613 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
615 /* IDSEL 0x0 */
616 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
617 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
618 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
619 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
621 pcie@0 {
622 reg = <0x0 0x0 0x0 0x0 0x0>;
626 ranges = <0x2000000 0x0 0x80000000
627 0x2000000 0x0 0x80000000
628 0x0 0x40000000
630 0x1000000 0x0 0x0
631 0x1000000 0x0 0x0
632 0x0 0x100000>;