Lines Matching +full:0 +full:xc300
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
30 #size-cells = <0>;
32 pmcslot@0 {
33 cell-index = <0>;
44 #size-cells = <0>;
46 xmcslot@0 {
47 cell-index = <0>;
65 #size-cells = <0>;
67 PowerPC,8572@0 {
69 reg = <0x0>;
72 d-cache-size = <0x8000>; // L1, 32K
73 i-cache-size = <0x8000>; // L1, 32K
74 timebase-frequency = <0>;
75 bus-frequency = <0>;
76 clock-frequency = <0>;
82 reg = <0x1>;
85 d-cache-size = <0x8000>; // L1, 32K
86 i-cache-size = <0x8000>; // L1, 32K
87 timebase-frequency = <0>;
88 bus-frequency = <0>;
89 clock-frequency = <0>;
96 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
103 reg = <0 0xef005000 0 0x1000>;
107 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
108 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
109 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
110 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
112 nor-boot@0,0 {
115 reg = <0 0 0x8000000>; /* 128MB */
118 partition@0 {
120 reg = <0x00000000 0x6f00000>; /* 111 MB */
124 reg = <0x6f00000 0x1000000>; /* 16 MB */
128 reg = <0x7f00000 0x40000>; /* 256 KB */
132 reg = <0x7f40000 0x40000>; /* 256 KB */
136 reg = <0x7f80000 0x80000>; /* 512 KB */
141 nor-alternate@1,0 {
144 //reg = <0xf0000000 0x08000000>; /* 128MB */
145 reg = <1 0 0x8000000>; /* 128MB */
148 partition@0 {
150 reg = <0x00000000 0x6f00000>; /* 111 MB */
154 reg = <0x6f00000 0x1000000>; /* 16 MB */
158 reg = <0x7f00000 0x40000>; /* 256 KB */
162 reg = <0x7f40000 0x40000>; /* 256 KB */
166 reg = <0x7f80000 0x80000>; /* 512 KB */
171 nand@2,0 {
182 reg = <2 0 0x40000>;
184 partition@0 {
186 reg = <0 0x40000000>;
197 ranges = <0x0 0 0xef000000 0x100000>;
198 bus-frequency = <0>; // Filled out by uboot.
200 ecm-law@0 {
202 reg = <0x0 0x1000>;
208 reg = <0x1000 0x1000>;
215 reg = <0x2000 0x1000>;
222 reg = <0x6000 0x1000>;
229 reg = <0x20000 0x1000>;
231 cache-size = <0x100000>; // L2, 1M
238 #size-cells = <0>;
239 cell-index = <0>;
241 reg = <0x3000 0x100>;
248 reg = <0x48>;
253 reg = <0x4c>;
258 reg = <0x51>;
263 reg = <0x54>;
269 reg = <0x68>;
274 reg = <0x70>;
279 reg = <0x18>;
282 polarity = <0x00>;
287 reg = <0x1c>;
290 polarity = <0x00>;
295 reg = <0x1e>;
298 polarity = <0x00>;
303 reg = <0x1f>;
306 polarity = <0x00>;
312 #size-cells = <0>;
315 reg = <0x3100 0x100>;
325 reg = <0xc300 0x4>;
326 ranges = <0x0 0xc100 0x200>;
328 dma-channel@0 {
331 reg = <0x0 0x80>;
332 cell-index = <0>;
339 reg = <0x80 0x80>;
347 reg = <0x100 0x80>;
355 reg = <0x180 0x80>;
366 reg = <0x21300 0x4>;
367 ranges = <0x0 0x21100 0x200>;
368 cell-index = <0>;
369 dma-channel@0 {
372 reg = <0x0 0x80>;
373 cell-index = <0>;
380 reg = <0x80 0x80>;
388 reg = <0x100 0x80>;
396 reg = <0x180 0x80>;
407 cell-index = <0>;
411 reg = <0x24000 0x1000>;
412 ranges = <0x0 0x24000 0x1000>;
422 #size-cells = <0>;
424 reg = <0x520 0x20>;
429 reg = <0x1>;
434 reg = <0x2>;
437 reg = <0x11>;
451 reg = <0x25000 0x1000>;
452 ranges = <0x0 0x25000 0x1000>;
462 #size-cells = <0>;
464 reg = <0x520 0x20>;
467 reg = <0x11>;
475 cell-index = <0>;
478 reg = <0x4500 0x100>;
479 clock-frequency = <0>;
489 reg = <0x4600 0x100>;
490 clock-frequency = <0>;
497 reg = <0xe0000 0x1000>;
503 reg = <0x41600 0x80>;
504 msi-available-ranges = <0 0x100>;
506 0xe0 0
507 0xe1 0
508 0xe2 0
509 0xe3 0
510 0xe4 0
511 0xe5 0
512 0xe6 0
513 0xe7 0>;
518 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
519 "fsl,sec2.1", "fsl,sec2.0";
520 reg = <0x30000 0x10000>;
525 fsl,exec-units-mask = <0x9fe>;
526 fsl,descriptor-types-mask = <0x3ab0ebf>;
531 #address-cells = <0>;
533 reg = <0x40000 0x40000>;
540 reg = <0xf000 0x1000>;
575 reg = <0x10000 0x5000>;
582 reg = <0x2f000 0x1000>;
589 reg = <0x15000 0x1000>;
602 reg = <0 0xef008000 0 0x1000>;
603 bus-range = <0 255>;
604 ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x10000000
605 0x1000000 0x0 0x00000000 0 0xe9000000 0x0 0x10000>;
609 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
611 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
612 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
613 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
614 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
616 pcie@0 {
617 reg = <0x0 0x0 0x0 0x0 0x0>;
621 ranges = <0x02000000 0x0 0xe0000000
622 0x02000000 0x0 0xe0000000
623 0x0 0x10000000
625 0x01000000 0x0 0x0
626 0x01000000 0x0 0x0
627 0x0 0x100000>;
638 reg = <0 0xef009000 0 0x1000>;
639 bus-range = <0 255>;
640 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
641 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x10000>;
645 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
647 /* IDSEL 0x0 */
648 0x0 0x0 0x0 0x1 &mpic 0x4 0x1
649 0x0 0x0 0x0 0x2 &mpic 0x5 0x1
650 0x0 0x0 0x0 0x3 &mpic 0x6 0x1
651 0x0 0x0 0x0 0x4 &mpic 0x7 0x1
653 pcie@0 {
654 reg = <0x0 0x0 0x0 0x0 0x0>;
658 ranges = <0x2000000 0x0 0xc0000000
659 0x2000000 0x0 0xc0000000
660 0x0 0x10000000
662 0x1000000 0x0 0x0
663 0x1000000 0x0 0x0
664 0x0 0x100000>;
675 reg = <0 0xef00a000 0 0x1000>;
676 bus-range = <0 255>;
677 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
678 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
682 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
684 /* IDSEL 0x0 */
685 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
686 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
687 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
688 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
690 pcie@0 {
691 reg = <0x0 0x0 0x0 0x0 0x0>;
695 ranges = <0x2000000 0x0 0x80000000
696 0x2000000 0x0 0x80000000
697 0x0 0x40000000
699 0x1000000 0x0 0x0
700 0x1000000 0x0 0x0
701 0x0 0x100000>;