Lines Matching +full:nand +full:- +full:cache
1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "PMC/XMC";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
41 next-level-cache = <&L2>;
47 d-cache-line-size = <32>; // 32 bytes
48 i-cache-line-size = <32>; // 32 bytes
49 d-cache-size = <0x8000>; // L1, 32K
50 i-cache-size = <0x8000>; // L1, 32K
51 timebase-frequency = <0>;
52 bus-frequency = <0>;
53 clock-frequency = <0>;
54 next-level-cache = <&L2>;
60 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
64 #address-cells = <2>;
65 #size-cells = <1>;
66 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
69 interrupt-parent = <&mpic>;
73 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
74 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
76 nor-boot@0,0 {
77 compatible = "amd,s29gl01gp", "cfi-flash";
78 bank-width = <2>;
80 #address-cells = <1>;
81 #size-cells = <1>;
95 label = "Primary U-Boot environment";
99 label = "Primary U-Boot";
101 read-only;
105 nor-alternate@1,0 {
106 compatible = "amd,s29gl01gp", "cfi-flash";
107 bank-width = <2>;
110 #address-cells = <1>;
111 #size-cells = <1>;
125 label = "Secondary U-Boot environment";
129 label = "Secondary U-Boot";
131 read-only;
135 nand@2,0 {
136 #address-cells = <1>;
137 #size-cells = <1>;
144 compatible = "fsl,mpc8572-fcm-nand",
145 "fsl,elbc-fcm-nand";
147 /* U-Boot should fix this up if chip size > 1 GB */
149 label = "NAND Filesystem";
157 #address-cells = <1>;
158 #size-cells = <1>;
160 compatible = "fsl,mpc8572-immr", "simple-bus";
162 bus-frequency = <0>; // Filled out by uboot.
164 ecm-law@0 {
165 compatible = "fsl,ecm-law";
167 fsl,num-laws = <12>;
171 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
174 interrupt-parent = <&mpic>;
177 memory-controller@2000 {
178 compatible = "fsl,mpc8572-memory-controller";
180 interrupt-parent = <&mpic>;
184 memory-controller@6000 {
185 compatible = "fsl,mpc8572-memory-controller";
187 interrupt-parent = <&mpic>;
191 L2: l2-cache-controller@20000 {
192 compatible = "fsl,mpc8572-l2-cache-controller";
194 cache-line-size = <32>; // 32 bytes
195 cache-size = <0x100000>; // L2, 1M
196 interrupt-parent = <&mpic>;
201 #address-cells = <1>;
202 #size-cells = <0>;
203 cell-index = <0>;
204 compatible = "fsl-i2c";
207 interrupt-parent = <&mpic>;
210 temp-sensor@48 {
215 temp-sensor@4c {
220 cpu-supervisor@51 {
236 pcie-switch@70 {
244 #gpio-cells = <2>;
245 gpio-controller;
252 #gpio-cells = <2>;
253 gpio-controller;
260 #gpio-cells = <2>;
261 gpio-controller;
268 #gpio-cells = <2>;
269 gpio-controller;
275 #address-cells = <1>;
276 #size-cells = <0>;
277 cell-index = <1>;
278 compatible = "fsl-i2c";
281 interrupt-parent = <&mpic>;
286 #address-cells = <1>;
287 #size-cells = <1>;
288 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
291 cell-index = <1>;
292 dma-channel@0 {
293 compatible = "fsl,mpc8572-dma-channel",
294 "fsl,eloplus-dma-channel";
296 cell-index = <0>;
297 interrupt-parent = <&mpic>;
300 dma-channel@80 {
301 compatible = "fsl,mpc8572-dma-channel",
302 "fsl,eloplus-dma-channel";
304 cell-index = <1>;
305 interrupt-parent = <&mpic>;
308 dma-channel@100 {
309 compatible = "fsl,mpc8572-dma-channel",
310 "fsl,eloplus-dma-channel";
312 cell-index = <2>;
313 interrupt-parent = <&mpic>;
316 dma-channel@180 {
317 compatible = "fsl,mpc8572-dma-channel",
318 "fsl,eloplus-dma-channel";
320 cell-index = <3>;
321 interrupt-parent = <&mpic>;
327 #address-cells = <1>;
328 #size-cells = <1>;
329 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
332 cell-index = <0>;
333 dma-channel@0 {
334 compatible = "fsl,mpc8572-dma-channel",
335 "fsl,eloplus-dma-channel";
337 cell-index = <0>;
338 interrupt-parent = <&mpic>;
341 dma-channel@80 {
342 compatible = "fsl,mpc8572-dma-channel",
343 "fsl,eloplus-dma-channel";
345 cell-index = <1>;
346 interrupt-parent = <&mpic>;
349 dma-channel@100 {
350 compatible = "fsl,mpc8572-dma-channel",
351 "fsl,eloplus-dma-channel";
353 cell-index = <2>;
354 interrupt-parent = <&mpic>;
357 dma-channel@180 {
358 compatible = "fsl,mpc8572-dma-channel",
359 "fsl,eloplus-dma-channel";
361 cell-index = <3>;
362 interrupt-parent = <&mpic>;
369 #address-cells = <1>;
370 #size-cells = <1>;
371 cell-index = <0>;
377 local-mac-address = [ 00 00 00 00 00 00 ];
379 interrupt-parent = <&mpic>;
380 tbi-handle = <&tbi0>;
381 phy-handle = <&phy0>;
382 phy-connection-type = "sgmii";
385 #address-cells = <1>;
386 #size-cells = <0>;
387 compatible = "fsl,gianfar-mdio";
390 phy0: ethernet-phy@1 {
391 interrupt-parent = <&mpic>;
395 phy1: ethernet-phy@2 {
396 interrupt-parent = <&mpic>;
400 tbi0: tbi-phy@11 {
402 device_type = "tbi-phy";
409 #address-cells = <1>;
410 #size-cells = <1>;
411 cell-index = <1>;
417 local-mac-address = [ 00 00 00 00 00 00 ];
419 interrupt-parent = <&mpic>;
420 tbi-handle = <&tbi1>;
421 phy-handle = <&phy1>;
422 phy-connection-type = "sgmii";
425 #address-cells = <1>;
426 #size-cells = <0>;
427 compatible = "fsl,gianfar-tbi";
430 tbi1: tbi-phy@11 {
432 device_type = "tbi-phy";
439 cell-index = <0>;
443 clock-frequency = <0>;
445 interrupt-parent = <&mpic>;
450 cell-index = <1>;
454 clock-frequency = <0>;
456 interrupt-parent = <&mpic>;
459 global-utilities@e0000 { //global utilities block
460 compatible = "fsl,mpc8572-guts";
462 fsl,has-rstcr;
466 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
468 msi-available-ranges = <0 0x100>;
478 interrupt-parent = <&mpic>;
486 interrupt-parent = <&mpic>;
487 fsl,num-channels = <4>;
488 fsl,channel-fifo-len = <24>;
489 fsl,exec-units-mask = <0x9fe>;
490 fsl,descriptor-types-mask = <0x3ab0ebf>;
494 interrupt-controller;
495 #address-cells = <0>;
496 #interrupt-cells = <2>;
498 compatible = "chrp,open-pic";
499 device_type = "open-pic";
503 compatible = "fsl,mpc8572-gpio";
506 interrupt-parent = <&mpic>;
507 #gpio-cells = <2>;
508 gpio-controller;
511 gpio-leds {
512 compatible = "gpio-leds";
517 linux,default-trigger = "heartbeat";
536 /* PME (pattern-matcher) */
538 compatible = "fsl,mpc8572-pme", "pme8572";
541 interrupt-parent = <&mpic>;
545 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
548 interrupt-parent = <&mpic>;
552 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
555 interrupt-parent = <&mpic>;
566 compatible = "fsl,mpc8548-pcie";
568 #interrupt-cells = <1>;
569 #size-cells = <2>;
570 #address-cells = <3>;
572 bus-range = <0 255>;
575 clock-frequency = <33333333>;
576 interrupt-parent = <&mpic>;
578 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
579 interrupt-map = <
588 #size-cells = <2>;
589 #address-cells = <3>;
603 compatible = "fsl,mpc8548-pcie";
605 #interrupt-cells = <1>;
606 #size-cells = <2>;
607 #address-cells = <3>;
609 bus-range = <0 255>;
612 clock-frequency = <33333333>;
613 interrupt-parent = <&mpic>;
615 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
616 interrupt-map = <
625 #size-cells = <2>;
626 #address-cells = <3>;