Lines Matching +full:0 +full:xc300
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
29 #size-cells = <0>;
31 PowerPC,8572@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
46 reg = <0x1>;
49 d-cache-size = <0x8000>; // L1, 32K
50 i-cache-size = <0x8000>; // L1, 32K
51 timebase-frequency = <0>;
52 bus-frequency = <0>;
53 clock-frequency = <0>;
60 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
67 reg = <0 0xef005000 0 0x1000>;
71 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
72 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
73 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
74 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
76 nor-boot@0,0 {
79 reg = <0 0 0x8000000>; /* 128MB */
82 partition@0 {
84 reg = <0x00000000 0x6f00000>; /* 111 MB */
88 reg = <0x6f00000 0x1000000>; /* 16 MB */
92 reg = <0x7f00000 0x40000>; /* 256 KB */
96 reg = <0x7f40000 0x40000>; /* 256 KB */
100 reg = <0x7f80000 0x80000>; /* 512 KB */
105 nor-alternate@1,0 {
108 //reg = <0xf0000000 0x08000000>; /* 128MB */
109 reg = <1 0 0x8000000>; /* 128MB */
112 partition@0 {
114 reg = <0x00000000 0x6f00000>; /* 111 MB */
118 reg = <0x6f00000 0x1000000>; /* 16 MB */
122 reg = <0x7f00000 0x40000>; /* 256 KB */
126 reg = <0x7f40000 0x40000>; /* 256 KB */
130 reg = <0x7f80000 0x80000>; /* 512 KB */
135 nand@2,0 {
146 reg = <2 0 0x40000>;
148 partition@0 {
150 reg = <0 0x40000000>;
161 ranges = <0x0 0 0xef000000 0x100000>;
162 bus-frequency = <0>; // Filled out by uboot.
164 ecm-law@0 {
166 reg = <0x0 0x1000>;
172 reg = <0x1000 0x1000>;
179 reg = <0x2000 0x1000>;
186 reg = <0x6000 0x1000>;
193 reg = <0x20000 0x1000>;
195 cache-size = <0x100000>; // L2, 1M
202 #size-cells = <0>;
203 cell-index = <0>;
205 reg = <0x3000 0x100>;
212 reg = <0x48>;
217 reg = <0x4c>;
222 reg = <0x51>;
227 reg = <0x54>;
233 reg = <0x68>;
238 reg = <0x70>;
243 reg = <0x18>;
246 polarity = <0x00>;
251 reg = <0x1c>;
254 polarity = <0x00>;
259 reg = <0x1e>;
262 polarity = <0x00>;
267 reg = <0x1f>;
270 polarity = <0x00>;
276 #size-cells = <0>;
279 reg = <0x3100 0x100>;
289 reg = <0xc300 0x4>;
290 ranges = <0x0 0xc100 0x200>;
292 dma-channel@0 {
295 reg = <0x0 0x80>;
296 cell-index = <0>;
303 reg = <0x80 0x80>;
311 reg = <0x100 0x80>;
319 reg = <0x180 0x80>;
330 reg = <0x21300 0x4>;
331 ranges = <0x0 0x21100 0x200>;
332 cell-index = <0>;
333 dma-channel@0 {
336 reg = <0x0 0x80>;
337 cell-index = <0>;
344 reg = <0x80 0x80>;
352 reg = <0x100 0x80>;
360 reg = <0x180 0x80>;
371 cell-index = <0>;
375 reg = <0x24000 0x1000>;
376 ranges = <0x0 0x24000 0x1000>;
386 #size-cells = <0>;
388 reg = <0x520 0x20>;
393 reg = <0x1>;
398 reg = <0x2>;
401 reg = <0x11>;
415 reg = <0x25000 0x1000>;
416 ranges = <0x0 0x25000 0x1000>;
426 #size-cells = <0>;
428 reg = <0x520 0x20>;
431 reg = <0x11>;
439 cell-index = <0>;
442 reg = <0x4500 0x100>;
443 clock-frequency = <0>;
453 reg = <0x4600 0x100>;
454 clock-frequency = <0>;
461 reg = <0xe0000 0x1000>;
467 reg = <0x41600 0x80>;
468 msi-available-ranges = <0 0x100>;
470 0xe0 0
471 0xe1 0
472 0xe2 0
473 0xe3 0
474 0xe4 0
475 0xe5 0
476 0xe6 0
477 0xe7 0>;
482 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
483 "fsl,sec2.1", "fsl,sec2.0";
484 reg = <0x30000 0x10000>;
489 fsl,exec-units-mask = <0x9fe>;
490 fsl,descriptor-types-mask = <0x3ab0ebf>;
495 #address-cells = <0>;
497 reg = <0x40000 0x40000>;
504 reg = <0xf000 0x1000>;
539 reg = <0x10000 0x5000>;
546 reg = <0x2f000 0x1000>;
553 reg = <0x15000 0x1000>;
571 reg = <0 0xef009000 0 0x1000>;
572 bus-range = <0 255>;
573 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
574 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>;
578 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
580 /* IDSEL 0x0 */
581 0x0 0x0 0x0 0x1 &mpic 0x4 0x1
582 0x0 0x0 0x0 0x2 &mpic 0x5 0x1
583 0x0 0x0 0x0 0x3 &mpic 0x6 0x1
584 0x0 0x0 0x0 0x4 &mpic 0x7 0x1
586 pcie@0 {
587 reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
591 ranges = <0x2000000 0x0 0xc0000000
592 0x2000000 0x0 0xc0000000
593 0x0 0x10000000
595 0x1000000 0x0 0x0
596 0x1000000 0x0 0x0
597 0x0 0x100000>;
608 reg = <0 0xef00a000 0 0x1000>;
609 bus-range = <0 255>;
610 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
611 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
615 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
617 /* IDSEL 0x0 */
618 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
619 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
620 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
621 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
623 pcie@0 {
624 reg = <0x0 0x0 0x0 0x0 0x0>;
628 ranges = <0x2000000 0x0 0x80000000
629 0x2000000 0x0 0x80000000
630 0x0 0x40000000
632 0x1000000 0x0 0x0
633 0x1000000 0x0 0x0
634 0x0 0x100000>;