Lines Matching +full:3 +full:- +full:cell
1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
39 next-level-cache = <&L2>;
45 reg = <0x0 0x0>; // Filled in by U-Boot
49 #address-cells = <1>;
50 #size-cells = <1>;
53 bus-frequency = <0>;
54 compatible = "fsl,mpc8548-immr", "simple-bus";
56 ecm-law@0 {
57 compatible = "fsl,ecm-law";
59 fsl,num-laws = <12>;
63 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
66 interrupt-parent = <&mpic>;
69 memory-controller@2000 {
70 compatible = "fsl,mpc8548-memory-controller";
72 interrupt-parent = <&mpic>;
76 L2: l2-cache-controller@20000 {
77 compatible = "fsl,mpc8548-l2-cache-controller";
79 cache-line-size = <32>; // 32 bytes
80 cache-size = <0x80000>; // L2, 512K
81 interrupt-parent = <&mpic>;
85 /* On-card I2C */
87 #address-cells = <1>;
88 #size-cells = <0>;
89 cell-index = <0>;
90 compatible = "fsl-i2c";
93 interrupt-parent = <&mpic>;
101 * 3: XMC root complex indicator
110 #gpio-cells = <2>;
111 gpio-controller;
119 #gpio-cells = <2>;
120 gpio-controller;
141 /* Off-card I2C */
143 #address-cells = <1>;
144 #size-cells = <0>;
145 cell-index = <1>;
146 compatible = "fsl-i2c";
149 interrupt-parent = <&mpic>;
154 #address-cells = <1>;
155 #size-cells = <1>;
156 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
159 cell-index = <0>;
160 dma-channel@0 {
161 compatible = "fsl,mpc8548-dma-channel",
162 "fsl,eloplus-dma-channel";
164 cell-index = <0>;
165 interrupt-parent = <&mpic>;
168 dma-channel@80 {
169 compatible = "fsl,mpc8548-dma-channel",
170 "fsl,eloplus-dma-channel";
172 cell-index = <1>;
173 interrupt-parent = <&mpic>;
176 dma-channel@100 {
177 compatible = "fsl,mpc8548-dma-channel",
178 "fsl,eloplus-dma-channel";
180 cell-index = <2>;
181 interrupt-parent = <&mpic>;
184 dma-channel@180 {
185 compatible = "fsl,mpc8548-dma-channel",
186 "fsl,eloplus-dma-channel";
188 cell-index = <3>;
189 interrupt-parent = <&mpic>;
196 #address-cells = <1>;
197 #size-cells = <1>;
198 cell-index = <0>;
204 local-mac-address = [ 00 00 00 00 00 00 ];
206 interrupt-parent = <&mpic>;
207 tbi-handle = <&tbi0>;
208 phy-handle = <&phy0>;
211 #address-cells = <1>;
212 #size-cells = <0>;
213 compatible = "fsl,gianfar-mdio";
216 phy0: ethernet-phy@1 {
217 interrupt-parent = <&mpic>;
221 phy1: ethernet-phy@2 {
222 interrupt-parent = <&mpic>;
226 phy2: ethernet-phy@3 {
227 interrupt-parent = <&mpic>;
231 phy3: ethernet-phy@4 {
232 interrupt-parent = <&mpic>;
236 tbi0: tbi-phy@11 {
238 device_type = "tbi-phy";
245 #address-cells = <1>;
246 #size-cells = <1>;
247 cell-index = <1>;
253 local-mac-address = [ 00 00 00 00 00 00 ];
255 interrupt-parent = <&mpic>;
256 tbi-handle = <&tbi1>;
257 phy-handle = <&phy1>;
260 #address-cells = <1>;
261 #size-cells = <0>;
262 compatible = "fsl,gianfar-tbi";
265 tbi1: tbi-phy@11 {
267 device_type = "tbi-phy";
274 #address-cells = <1>;
275 #size-cells = <1>;
276 cell-index = <2>;
282 local-mac-address = [ 00 00 00 00 00 00 ];
284 interrupt-parent = <&mpic>;
285 tbi-handle = <&tbi2>;
286 phy-handle = <&phy2>;
289 #address-cells = <1>;
290 #size-cells = <0>;
291 compatible = "fsl,gianfar-tbi";
294 tbi2: tbi-phy@11 {
296 device_type = "tbi-phy";
301 /* eTSEC4: Rear panel port 3 */
303 #address-cells = <1>;
304 #size-cells = <1>;
305 cell-index = <3>;
311 local-mac-address = [ 00 00 00 00 00 00 ];
313 interrupt-parent = <&mpic>;
314 tbi-handle = <&tbi3>;
315 phy-handle = <&phy3>;
318 #address-cells = <1>;
319 #size-cells = <0>;
320 compatible = "fsl,gianfar-tbi";
323 tbi3: tbi-phy@11 {
325 device_type = "tbi-phy";
331 cell-index = <0>;
335 clock-frequency = <0>;
336 current-speed = <115200>;
338 interrupt-parent = <&mpic>;
342 cell-index = <1>;
346 clock-frequency = <0>;
347 current-speed = <115200>;
349 interrupt-parent = <&mpic>;
352 global-utilities@e0000 { // global utilities reg
353 compatible = "fsl,mpc8548-guts";
355 fsl,has-rstcr;
359 interrupt-controller;
360 #address-cells = <0>;
361 #interrupt-cells = <2>;
363 compatible = "chrp,open-pic";
364 device_type = "open-pic";
369 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
370 "simple-bus";
371 #address-cells = <2>;
372 #size-cells = <1>;
374 interrupt-parent = <&mpic>;
381 3 0x0 0xef840000 0x00010000 // NAND CE2
384 nor-boot@0,0 {
385 #address-cells = <1>;
386 #size-cells = <1>;
387 compatible = "cfi-flash";
389 bank-width = <2>;
403 partition@3f80000 {
409 nor-alternate@1,0 {
410 #address-cells = <1>;
411 #size-cells = <1>;
412 compatible = "cfi-flash";
414 bank-width = <2>;
420 partition@3f80000 {
427 #address-cells = <1>;
428 #size-cells = <1>;
429 compatible = "xes,address-ctl-nand";
431 cle-line = <0x8>; /* CLE tied to A3 */
432 ale-line = <0x10>; /* ALE tied to A4 */
434 /* U-Boot should fix this up */
444 #interrupt-cells = <1>;
445 #size-cells = <2>;
446 #address-cells = <3>;
447 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
450 clock-frequency = <33333333>;
451 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
452 interrupt-map = <
455 0xe000 0 0 2 &mpic 3 1>;
457 interrupt-parent = <&mpic>;
459 bus-range = <0 0>;
464 /* XMC PCIe is not yet enabled in U-Boot on XPedite5200 */