Lines Matching +full:2 +full:- +full:compatible
1 // SPDX-License-Identifier: GPL-2.0-only
6 * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
9 /dts-v1/;
12 compatible = "xes,xcalibur1501", "xes,MPC8572";
13 #address-cells = <2>;
14 #size-cells = <2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>; // 32 bytes
34 i-cache-line-size = <32>; // 32 bytes
35 d-cache-size = <0x8000>; // L1, 32K
36 i-cache-size = <0x8000>; // L1, 32K
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
40 next-level-cache = <&L2>;
46 d-cache-line-size = <32>; // 32 bytes
47 i-cache-line-size = <32>; // 32 bytes
48 d-cache-size = <0x8000>; // L1, 32K
49 i-cache-size = <0x8000>; // L1, 32K
50 timebase-frequency = <0>;
51 bus-frequency = <0>;
52 clock-frequency = <0>;
53 next-level-cache = <&L2>;
59 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
63 #address-cells = <2>;
64 #size-cells = <1>;
65 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
67 interrupts = <19 2>;
68 interrupt-parent = <&mpic>;
71 1 0 0 0xf0000000 0x8000000 /* CS1: Flash 2 */
72 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
76 nor-boot@0,0 {
77 compatible = "amd,s29gl01gp", "cfi-flash";
78 bank-width = <2>;
80 #address-cells = <1>;
81 #size-cells = <1>;
95 label = "Primary U-Boot environment";
99 label = "Primary U-Boot";
101 read-only;
105 nor-alternate@1,0 {
106 compatible = "amd,s29gl01gp", "cfi-flash";
107 bank-width = <2>;
110 #address-cells = <1>;
111 #size-cells = <1>;
125 label = "Secondary U-Boot environment";
129 label = "Secondary U-Boot";
131 read-only;
135 nand@2,0 {
136 #address-cells = <1>;
137 #size-cells = <1>;
140 * Micron MT29F8G08DAA (2x 512 MB), or Micron
141 * MT29F16G08FAA (2x 1 GB), depending on the build
144 compatible = "fsl,mpc8572-fcm-nand",
145 "fsl,elbc-fcm-nand";
146 reg = <2 0 0x40000>;
147 /* U-Boot should fix this up if chip size > 1 GB */
155 compatible = "nxp,usb-isp1761";
157 bus-width = <32>;
158 interrupt-parent = <&mpic>;
164 #address-cells = <1>;
165 #size-cells = <1>;
167 compatible = "fsl,mpc8572-immr", "simple-bus";
169 bus-frequency = <0>; // Filled out by uboot.
171 ecm-law@0 {
172 compatible = "fsl,ecm-law";
174 fsl,num-laws = <12>;
178 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
180 interrupts = <17 2>;
181 interrupt-parent = <&mpic>;
184 memory-controller@2000 {
185 compatible = "fsl,mpc8572-memory-controller";
187 interrupt-parent = <&mpic>;
188 interrupts = <18 2>;
191 memory-controller@6000 {
192 compatible = "fsl,mpc8572-memory-controller";
194 interrupt-parent = <&mpic>;
195 interrupts = <18 2>;
198 L2: l2-cache-controller@20000 {
199 compatible = "fsl,mpc8572-l2-cache-controller";
201 cache-line-size = <32>; // 32 bytes
202 cache-size = <0x100000>; // L2, 1M
203 interrupt-parent = <&mpic>;
204 interrupts = <16 2>;
208 #address-cells = <1>;
209 #size-cells = <0>;
210 cell-index = <0>;
211 compatible = "fsl-i2c";
213 interrupts = <43 2>;
214 interrupt-parent = <&mpic>;
217 temp-sensor@48 {
218 compatible = "dallas,ds1631", "dallas,ds1621";
222 temp-sensor@4c {
223 compatible = "adi,adt7461";
227 cpu-supervisor@51 {
228 compatible = "dallas,ds4510";
233 compatible = "atmel,at24c128b";
238 compatible = "st,m41t00",
243 pcie-switch@6a {
244 compatible = "plx,pex8648";
248 /* On-board signals for VID, flash, serial */
250 compatible = "nxp,pca9557";
252 #gpio-cells = <2>;
253 gpio-controller;
259 compatible = "nxp,pca9557";
261 #gpio-cells = <2>;
262 gpio-controller;
268 compatible = "nxp,pca9557";
270 #gpio-cells = <2>;
271 gpio-controller;
277 compatible = "nxp,pca9557";
279 #gpio-cells = <2>;
280 gpio-controller;
286 compatible = "nxp,pca9557";
288 #gpio-cells = <2>;
289 gpio-controller;
295 #address-cells = <1>;
296 #size-cells = <0>;
297 cell-index = <1>;
298 compatible = "fsl-i2c";
300 interrupts = <43 2>;
301 interrupt-parent = <&mpic>;
306 #address-cells = <1>;
307 #size-cells = <1>;
308 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
311 cell-index = <1>;
312 dma-channel@0 {
313 compatible = "fsl,mpc8572-dma-channel",
314 "fsl,eloplus-dma-channel";
316 cell-index = <0>;
317 interrupt-parent = <&mpic>;
318 interrupts = <76 2>;
320 dma-channel@80 {
321 compatible = "fsl,mpc8572-dma-channel",
322 "fsl,eloplus-dma-channel";
324 cell-index = <1>;
325 interrupt-parent = <&mpic>;
326 interrupts = <77 2>;
328 dma-channel@100 {
329 compatible = "fsl,mpc8572-dma-channel",
330 "fsl,eloplus-dma-channel";
332 cell-index = <2>;
333 interrupt-parent = <&mpic>;
334 interrupts = <78 2>;
336 dma-channel@180 {
337 compatible = "fsl,mpc8572-dma-channel",
338 "fsl,eloplus-dma-channel";
340 cell-index = <3>;
341 interrupt-parent = <&mpic>;
342 interrupts = <79 2>;
347 #address-cells = <1>;
348 #size-cells = <1>;
349 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
352 cell-index = <0>;
353 dma-channel@0 {
354 compatible = "fsl,mpc8572-dma-channel",
355 "fsl,eloplus-dma-channel";
357 cell-index = <0>;
358 interrupt-parent = <&mpic>;
359 interrupts = <20 2>;
361 dma-channel@80 {
362 compatible = "fsl,mpc8572-dma-channel",
363 "fsl,eloplus-dma-channel";
365 cell-index = <1>;
366 interrupt-parent = <&mpic>;
367 interrupts = <21 2>;
369 dma-channel@100 {
370 compatible = "fsl,mpc8572-dma-channel",
371 "fsl,eloplus-dma-channel";
373 cell-index = <2>;
374 interrupt-parent = <&mpic>;
375 interrupts = <22 2>;
377 dma-channel@180 {
378 compatible = "fsl,mpc8572-dma-channel",
379 "fsl,eloplus-dma-channel";
381 cell-index = <3>;
382 interrupt-parent = <&mpic>;
383 interrupts = <23 2>;
389 #address-cells = <1>;
390 #size-cells = <1>;
391 cell-index = <0>;
394 compatible = "gianfar";
397 local-mac-address = [ 00 00 00 00 00 00 ];
398 interrupts = <29 2 30 2 34 2>;
399 interrupt-parent = <&mpic>;
400 tbi-handle = <&tbi0>;
401 phy-handle = <&phy0>;
402 phy-connection-type = "sgmii";
405 #address-cells = <1>;
406 #size-cells = <0>;
407 compatible = "fsl,gianfar-mdio";
410 phy0: ethernet-phy@1 {
411 interrupt-parent = <&mpic>;
415 phy1: ethernet-phy@2 {
416 interrupt-parent = <&mpic>;
420 phy2: ethernet-phy@3 {
421 interrupt-parent = <&mpic>;
425 phy3: ethernet-phy@4 {
426 interrupt-parent = <&mpic>;
430 tbi0: tbi-phy@11 {
432 device_type = "tbi-phy";
437 /* eTSEC 2 front panel 1 */
439 #address-cells = <1>;
440 #size-cells = <1>;
441 cell-index = <1>;
444 compatible = "gianfar";
447 local-mac-address = [ 00 00 00 00 00 00 ];
448 interrupts = <35 2 36 2 40 2>;
449 interrupt-parent = <&mpic>;
450 tbi-handle = <&tbi1>;
451 phy-handle = <&phy1>;
452 phy-connection-type = "sgmii";
455 #address-cells = <1>;
456 #size-cells = <0>;
457 compatible = "fsl,gianfar-tbi";
460 tbi1: tbi-phy@11 {
462 device_type = "tbi-phy";
469 #address-cells = <1>;
470 #size-cells = <1>;
471 cell-index = <2>;
474 compatible = "gianfar";
477 local-mac-address = [ 00 00 00 00 00 00 ];
478 interrupts = <31 2 32 2 33 2>;
479 interrupt-parent = <&mpic>;
480 tbi-handle = <&tbi2>;
481 phy-handle = <&phy2>;
482 phy-connection-type = "sgmii";
485 #address-cells = <1>;
486 #size-cells = <0>;
487 compatible = "fsl,gianfar-tbi";
490 tbi2: tbi-phy@11 {
492 device_type = "tbi-phy";
499 #address-cells = <1>;
500 #size-cells = <1>;
501 cell-index = <3>;
504 compatible = "gianfar";
507 local-mac-address = [ 00 00 00 00 00 00 ];
508 interrupts = <37 2 38 2 39 2>;
509 interrupt-parent = <&mpic>;
510 tbi-handle = <&tbi3>;
511 phy-handle = <&phy3>;
512 phy-connection-type = "sgmii";
515 #address-cells = <1>;
516 #size-cells = <0>;
517 compatible = "fsl,gianfar-tbi";
520 tbi3: tbi-phy@11 {
522 device_type = "tbi-phy";
529 cell-index = <0>;
531 compatible = "fsl,ns16550", "ns16550";
533 clock-frequency = <0>;
534 interrupts = <42 2>;
535 interrupt-parent = <&mpic>;
540 cell-index = <1>;
542 compatible = "fsl,ns16550", "ns16550";
544 clock-frequency = <0>;
545 interrupts = <42 2>;
546 interrupt-parent = <&mpic>;
549 global-utilities@e0000 { //global utilities block
550 compatible = "fsl,mpc8572-guts";
552 fsl,has-rstcr;
556 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
558 msi-available-ranges = <0 0x100>;
568 interrupt-parent = <&mpic>;
572 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
575 interrupts = <45 2 58 2>;
576 interrupt-parent = <&mpic>;
577 fsl,num-channels = <4>;
578 fsl,channel-fifo-len = <24>;
579 fsl,exec-units-mask = <0x9fe>;
580 fsl,descriptor-types-mask = <0x3ab0ebf>;
584 interrupt-controller;
585 #address-cells = <0>;
586 #interrupt-cells = <2>;
588 compatible = "chrp,open-pic";
589 device_type = "open-pic";
593 compatible = "fsl,mpc8572-gpio";
595 interrupts = <47 2>;
596 interrupt-parent = <&mpic>;
597 #gpio-cells = <2>;
598 gpio-controller;
601 gpio-leds {
602 compatible = "gpio-leds";
607 linux,default-trigger = "heartbeat";
626 /* PME (pattern-matcher) */
628 compatible = "fsl,mpc8572-pme", "pme8572";
630 interrupts = <57 2 64 2 65 2 66 2 67 2>;
631 interrupt-parent = <&mpic>;
634 tlu@2f000 {
635 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
637 interrupts = <61 2>;
638 interrupt-parent = <&mpic>;
642 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
644 interrupts = <75 2>;
645 interrupt-parent = <&mpic>;
653 * PCI Express controller 2 @ ef009000 is not used.
659 compatible = "fsl,mpc8548-pcie";
661 #interrupt-cells = <1>;
662 #size-cells = <2>;
663 #address-cells = <3>;
665 bus-range = <0 255>;
668 clock-frequency = <33333333>;
669 interrupt-parent = <&mpic>;
670 interrupts = <26 2>;
671 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
672 interrupt-map = <
681 #size-cells = <2>;
682 #address-cells = <3>;